f*********r
发帖数: 674 | 1 Description
Responsibilities:
* Verification of a high performance CPU pipeline at a core/FC level
both
architecturally and micro-architecturally
* Development and maintenance of test generation tools for the CPU
at pre-silicon and post-silicon levels.
* Work closely with other verification engineers to incorporate testing
feedback into the test generation tool
* Understand micro-architecture of the block to be verified, and develop
and execute
testplans for the same
* Own and debug failures in simulation to root-cause problems
* Closely work with RTL engineers of block being verified for testplan
development, execution, and debug
Requirements:
* Good CPU architecture/micro-architecture knowledge (one of MIPS/
PowerPC/ARM/x86/SPARC architectures, CPU pipeline, out-of-order, superscalar
, caches)
* Strong programming knowledge and experience in C++
* Working knowledge of Verilog
* Good verification skills and knowledge of different verification
methodologies
* Knowledge of unix/linux environment and scripting (perl/python)
* BS (EE or CS) required with 3-8 years relevant experience. MS (EE or
CS) preferred
* Self-motivated team player with excellent problem solving skills |
|
