Couple ASIC design and/or Verification engineer openings - JobHunting版

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JobHunting版 - Couple ASIC design and/or Verification engineer openings

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话题: asic话题: couple话题: design话题: openings

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(共1页)

s******n
发帖数: 44

1. In silicon valley
2. Skills requirement: verilog, system verilog, design compiler
3. Communication DSP background is a plus
4. Fresh MS or PhD is okey
Please respond with your resume if you are interested.

(共1页)

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话题: asic话题: couple话题: design话题: openings

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