w*******y
发帖数: 60932 | 1 Sierra Trading Post has some great deals on Asics Gel Running Shoes. Some
colors and styles have limited sizes. Use coupon "ALFALL1" for 20% off.
Shipping starts at $7.95. Or use code EB091311B for 35% off your order plus
free ground shipping if you are spending more than $100. I was able to get a
pair of Kanbarra 5s, Enduro 6s, and Equation 4s for $89.61 shipped. Came
out to $28.87 a pair!
Prices below reflect 20% discount. Will be cheaper if you use the 35% off
code.
Asics Gel Kanbarra 5 Runni... 阅读全帖 |
|
|
m*****t
发帖数: 3477 | 3 【 以下文字转载自 JobHunting 讨论区 】
发信人: TroubleT (大麻烦), 信区: JobHunting
标 题: Couple ASIC Openings ( San Jose)
发信站: BBS 未名空间站 (Wed Mar 23 18:53:40 2011, 美东)
Hello, these just opened up, please submit via company website here :
http://tbe.taleo.net/NA1/ats/careers/searchResults.jsp?org=ATHE
Sr. Digital IC Verification Engineer
Responsibilities:
This position requires working with our architecture, design, and
verification teams to develop simulation and verification environments that
prove correctness a... 阅读全帖 |
|
|
i******y
发帖数: 48 | 5 FPGA/ASIC Design Engineer
Location: Southern California, CA
The FPGA/ASIC Design Engineer is responsible for the design of control, and
manufacturing chip systems utilizing advance high density FPGA products and
transition to ASIC/SoC design. This includes all areas of digital design of
FPGA/ASIC development including chip architecture, RTL, implementation, RTL
synthesis, validation, and lab bring-up and characterization. The Engineer
works with advanced development teams on developing next gen... 阅读全帖 |
|
i******y
发帖数: 48 | 6 FPGA/ASIC Design Engineer
Location: Southern California, CA
The FPGA/ASIC Design Engineer is responsible for the design of control, and
manufacturing chip systems utilizing advance high density FPGA products and
transition to ASIC/SoC design. This includes all areas of digital design of
FPGA/ASIC development including chip architecture, RTL, implementation, RTL
synthesis, validation, and lab bring-up and characterization. The Engineer
works with advanced development teams on developing next gen... 阅读全帖 |
|
p*******r
发帖数: 16 | 7 楼主所在的组是Apple的SOC核心部门，现在扩招，至少有两个Junior ASIC Design
Engineer的open。楼主是TL，这两个open都是参与楼主负责的project。目前迫切需要
的是Junior 的 ASIC Designer (1-3 yrs experience) 的 candidate。希望你对ASIC
Design， RTL coding， scripting和一些architecture感兴趣，愿意学习和承担task
General JD as follows:
https://jobs.apple.com/en-us/details/200001929/asic-design-engineer?team=
HRDWR
Key Qualifications
RTL Logic Design experience of multi-million gate ASICs
Hands-on experience in all aspects of the chip development process with
proficiency in front-e... 阅读全帖 |
|
w*******y
发帖数: 60932 | 8 These Asics shoes are on sale for $34.99 plus you get an additional 15% off
after you add it to your cart plus free shipping to home
Final price is $29.74
Asics Men's Gel Enduro 6 - Silver:
http://www.sears.com/shc/s/p_10153_12605_07690289000P?prdNo=18
Next best on google products is $49.99:
http://www.google.com/search?q=Asics Men's Gel Enduro 6&hl=en&client=opera&hs=LZ0&rls=en&channel=suggest&prmd=ivns&source=univ&tbs=shop:1&tbo=u&ei=dsQoTYaFCYz6sAPIkKyGBw&sa=X&oi=product_result_group&ct=title... 阅读全帖 |
|
s****3
发帖数: 257 | 9 我是用FPGA做些DSP 算法实现的，这个职位是ASIC Design Engineer. 我没有过什么流
片经历，我觉得这种经历也没太多PHD会有。感觉自己只是在用FPGA/ASIC 做为TOOL来
设计DSP 算法，根本就和DESIGN FPGA/ASIC 没多大关系。但是我也只能投这样的工作
，别的我也TMD不会啊。凡是把DSP算法 和FPGA联系起来的工作都要CITIZENSHIP，我结
婚了，没办法了，错过机会了。
大家说说像ASIC/FPGA DESIGN ENGINEER这样的工作是不是必须要求有真正设计CHIP的
经历啊？光是有ASIC/FPGA当TOOL的经历是不够的？ |
|
c*********g
发帖数: 14 | 10 We have a few openings at our San Jose office. If you are interested (or
your friends may be interested), please feel free to send your resumes to :
c**********[email protected]
Thank you very much
Company: MediaTek USA, Inc
Job position: multiple ASIC architecture, system modeling, Design engineer(
DE) engineering positions available from mid to senior level.
Job titles: Staff Engineer, Technical Manager.
Job Requirements:
- Minimum 5 years of ASIC Design experience with BSEE or MSEE de... 阅读全帖 |
|
M*****8
发帖数: 49 | 11 本人初入职场，EE出身，向各位大神请教一下ASIC的前景。
看到现在Google,Facebook,Microsoft等软件巨头也有若干ASIC的职位,请问package是
否和码农差不多？
借着AI芯片和挖矿机的热潮，ASIC行业未来发展会是硬件中最好的吗？
ASIC这行竞争没有码农激烈，是否上升空间会更多？是否青春饭？
感谢各位的指点和建议！ |
|
a***a
发帖数: 4195 | 12 最近跑步的鞋子穿帮了，就随手买了一个耐克的跑鞋。 结果花了70多刀，买了个脑震
荡鞋，每一次脚落地的震动全都用来搅脑浆了，跑完一圈差点没吐了，实在是太难受了
。后来研究了一把，大家都说 Asics 跑鞋好，就是太贵，一咬牙,一跺脚，一个月不吃
午饭，买了一个160块钱的 Asics GEL-Kayano。 不一样就是不一样啊，跑起来腾云驾
雾的。
以前没怎么听说 Asics 鞋，现在看来还真不错。
下一个羽毛鞋准备搞个价廉物美的 Asics 排球女将鞋！ |
|
m***8
发帖数: 1786 | 13 比特币是最早的数字货币，只要算力，可以堆核傻算，所以算法简单，开发ASIC难度低
，几个工程师就行了。每一代产品更新其实是台积电等公司芯片制造进程的更新，ASIC
设计变动不大。
在研究新的币种时，算法加大了难度，比如第二有名的数字货币以太币，挖币仅仅堆核
傻算没用，要用到大量存储器访问，这种技术世界上目前只有那几个大公司拥有，中小
规模的公司基本上不可能设计出来与之相比，所以估计三五年不会有以太币的ASIC出现。
：据说ASIC的算力是GPU的100倍
： |
|
M*****8
发帖数: 49 | 14 本人初入职场，EE出身，向各位大神请教一下ASIC的前景。
看到现在Google,Facebook,Microsoft等软件巨头也有若干ASIC的职位,请问package是
否和码农差不多？
借着AI芯片和挖矿机的热潮，ASIC行业未来发展会是硬件中最好的吗？
ASIC这行竞争没有码农激烈，是否上升空间会更多？是否青春饭？
感谢各位的指点和建议！ |
|
|
w*******y
发帖数: 60932 | 16 Apply Coupon Code = SDSALEAsics
Men's Active Running Watch for $19
Asics
Men's Active Running Watch for $19
Wittnauer
Women's Watch for $45
Asics
Men's Active Running Watch for $25
Asics
Men's Active Running Watch for $25
Joy Watches
Women's Rectangulares Watch for $29
Joy Watches
Women's Ovalados Watch for $35
Joy Watches
Women's Ovalados Watch for $40
Wittnauer
Men's Watch for $49
Asics
Men's Chronograph Watch for $50
Bulova
Men's Dress Watch for $50
|
|
w*******y
发帖数: 60932 | 17 ASICS Men's Hooded Sweatshirt
Black , Heather, Navy
Size from XS-XXXL
15.00 FS with Prime.
They don't have a picture but from the model number Asics site shows:
reference:
http://www.asicsamerica.com/Apparel/Warm-Up-/Hooded-Logo-Sweats
Snug and cozy. That's what a great sweatshirt should be. But throw in a
cotton/fleece construction, cold weather hood, and the stylish good looks of
the ASICS embroidered logo, and suddenly you've got something awesome.
High quality stitching and detailing
... 阅读全帖 |
|
|
l**t
发帖数: 10440 | 19 Senior ASIC Verification Engineer in Marvell Semiconductor:
Resposibilities include:
*Participate in early reviews of IP definition and architecture development
*Develop verification testplan for new design, build test bench, models,
test cases
*Interact with design team
*Perform rtl code coverage
Desired Skills & Experience:
*BS/MS degree in EE or CS with 5+ years of working experience in
Verification.
*Must have knowledge and experience of ASIC verification flows and
methodologies*Good Knowled... 阅读全帖 |
|
H******d
发帖数: 98 | 20 各位前辈们好！小弟在加州系统的top3学校读ECE硕士，已毕业，主攻ASIC数字电路方
向，基本Hardware相关的技能、仪器我都会。
去年在Broadcom实习半年，做的是ASIC Design and Verification Intern，认真负责
，吃苦耐劳，上手快。
今年年初网投了几个月也没多少消息，所以恳请各位前辈内推一下ASIC/VLSI相关的
full
time职位，Design/Verification/Validation/Application Engineer这些都没问题，
小弟必知恩图报！
可站内联系我或者邮箱 i*******[email protected] 在此谢谢各位！ |
|
p*******r
发帖数: 16 | 21 Apple（我所在的组）招 ASIC Engineer，是做front end的design，有好几个opening
，非常希望国人加入！如果感兴趣请发简历至p*******[email protected]. 简历楼主会筛选
一下，如果没问题可以直接递给hiring manager.
如果是new grad，只需要名校＋high GPA，这样容易过简历关
如果是有经验的在职跳槽，需要对Front End的design process 包括 coding micro
architecture synthesis timing CDC等等都有很好的理解
familiar with AXI protocol and design is a plus.
不需要太多的 data process knowledge but need to be excellent about control
flow and handshake
具体如下
Key Qualification:
RTL Logic Design experience of multi-million gate ASICs
Hands on e... 阅读全帖 |
|
d********g
发帖数: 42 | 22 ASIC is a fucking shit hole, I had 5 years ASIC design experience and PhD
in EE, made the same salary as an entry level Software Kid. I switched to
software a couple of years ago, package doubled since then. so stay away
from ASIC, use your spare time doing leetcode and jump ASAP |
|
H**********5
发帖数: 2012 | 23 一入肛门深似海10个字
: ASIC is a fucking shit hole, I had 5 years ASIC design experience and
PhD
: in EE, made the same salary as an entry level Software Kid. I
switched to
: software a couple of years ago, package doubled since then. so stay
away
: from ASIC, use your spare time doing leetcode and jump ASAP
|
|
m******8
发帖数: 3 | 24 Job Title: Engineer, ASIC Design
Qualifications: The candidate must have extensive experience in efficient
architecture derivation of DSP and communications algorithms.
The candidate must be proficient in C/C++ and MATLAB programming.
The candidate must be proficient in RTL coding and experience in developing
ASICs.
Ph.D or M.S. degree in EE + 5 years of experience.
Description: This position is responsible to derive efficient ASIC
architectures for sophisticated DSP and communication algorit |
|
s**********e
发帖数: 2 | 25 北京某IC设计外企高薪急聘ASIC/SoC设计总监，要求如下：
- 成功大规模量产过通信芯片，有5年以上大规模ASIC芯片设计经验
- 有丰富的ASIC设计经验，包括：Verilog/VHDL modeling, design, simulation and
verification; block synthesis and timing check; power estimation and low
power design; DFT techniques；PHY RTL design；SoC design
- 有项目管理经验
- 熟悉DSP，能与算法及FPGA工程师一起进行系统设计
- 硕士及以上学历
- 能长期在北京工作
本职位年薪$100K。请将简历发到邮箱 i******[email protected]. |
|
r*****n
发帖数: 964 | 26 替同学发帖
公司在上海，公司核心技术是DSP系统，业务开展的很好，目前向ASIC方向延伸，做一
些DSP相关的芯片。由于和一些研究所关系很好，加上技术力量强，已经作为主申请人
承接了几个国家项目。项目总资金额在1亿左右。也有券商在开始创业板的接触。
现在已经有了一个10人ASIC团队（另外还有软件，电路板设计团队）。团队成员都在国
内著名芯片设计公司工作过。已经tapeout了一块芯片。
我同学是公司老总，很想能作出一点事业，希望能有志同道合者加盟。合作方式最好是
能回国一起创业；也可以考虑留在硅谷，以顾问的形式合作。他这个月会来bay area，
具体可以面谈。有意者可以发信给我。q**********[email protected]
希望合作者
至少有5年ASIC工作经验，3 tapeout experience
精通DSP/CPU architecture |
|
H******d
发帖数: 98 | 27 各位前辈们好！小弟在加州系统的top3学校读ECE硕士，已毕业，主攻ASIC数字电路方
向，基本Hardware相关的技能、仪器我都会。
去年在Broadcom实习半年，做的是ASIC Design and Verification Intern，认真负责
，吃苦耐劳，上手快。
今年年初网投了几个月也没多少消息，所以恳请各位前辈内推一下ASIC相关的full
time职位，Design/Verification/Validation/Application Engineer这些都没问题，
小弟必知恩图报！
可站内联系我或者邮箱 i*******[email protected] 在此谢谢各位！ |
|
l**t
发帖数: 10440 | 28 Senior ASIC Verification Engineer in Marvell Semiconductor:
Resposibilities include:
*Participate in early reviews of IP definition and architecture development
*Develop verification testplan for new design, build test bench, models,
test cases
*Interact with design team
*Perform rtl code coverage
Desired Skills & Experience:
*BS/MS degree in EE or CS with 5+ years of working experience in
Verification.
*Must have knowledge and experience of ASIC verification flows and
methodologies*Good Knowled... 阅读全帖 |
|
s**********n
发帖数: 2343 | 29 【 以下文字转载自 WaterWorld 讨论区 】
发信人: semijob (semijob), 信区: WaterWorld
标 题: 请转EE版, San Francisco 版： ASIC Design/Implementation Job Opening
关键字: Job Opening
发信站: BBS 未名空间站 (Fri Nov 4 13:23:02 2011, 美东)
A Fabless Semiconductor company in San Jose, CA is looking for a senior
level ASIC design/implementation engineer. The person will be responsible
for ASIC implementation including synthesis, DFT, timing closure, place &
route. RTL design experience is a plus.Will be involved to work with CAD tool vend... 阅读全帖 |
|
h******1
发帖数: 1930 | 30 各位大牛好！
小弟初来乍到，冒个泡求问一下鞋子的问题。
来美好几年了，没打几次球。最近有点时间了，刚巧也找到了球友，所以去的勤了。
一双科6，干什么都穿它，最近底已经磨的不行了，在木地板上直出溜。。
刚刚考古了一下精华区，看了大家对鞋子的一些评价，感觉yy和Asics都各有长短。
我预算大家就不超过80块钱。找了这么两双，大家看看哪个比较好？
yy SHB-45
Asics GEL-Rocket 7
Asics是在onlineshoes.com 上看到的，似乎质保更好？
另，我一般穿鞋都是42号，脚比较宽，请问买羽球些8码半的可以吗？
不胜感激！ |
|
d**********0
发帖数: 13081 | 31 =========================================
kayano 是Asics 中的顶级稳定型跑鞋,体重大的人应该穿这个,保护膝盖.他的Duomax/.
Gel用的不错.
((不过要是体重过重了超过85kg,还是要先减下来再考虑跑步,毕竟跑步多少对膝盖还是
有一些损伤的.))
现在K14好像很少了,基本上被败光了,K15还有在卖,最低好像5-6折可以拿到.
Asics鞋的包裹性和舒适度是没得说的.
但是Asics也有个缺陷,透气性比较失败,K15上面还有一块是皮质的.透气性甚是失败.
NB 的1225也不错,在鞋宽方便也可以多样选择.跑起来也不错.可以考虑一下.不过价格
方面没有什么优势. |
|
d**********0
发帖数: 13081 | 32 =========================================
kayano 是Asics 中的顶级稳定型跑鞋,体重大的人应该穿这个,保护膝盖.他的Duomax/.
Gel用的不错.
((不过要是体重过重了超过85kg,还是要先减下来再考虑跑步,毕竟跑步多少对膝盖还是
有一些损伤的.))
现在K14好像很少了,基本上被败光了,K15还有在卖,最低好像5-6折可以拿到.
Asics鞋的包裹性和舒适度是没得说的.
但是Asics也有个缺陷,透气性比较失败,K15上面还有一块是皮质的.透气性甚是失败.
NB 的1225也不错,在鞋宽方便也可以多样选择.跑起来也不错.可以考虑一下.不过价格
方面没有什么优势. |
|
d**********0
发帖数: 13081 | 33 ASICS Men's GEL-Venture 4 Running Shoes From $31 + Free Shipping
ASICS Men's GEL-Venture 4 Running Shoes
Buy Now ►
Amazon.com has various ASICS Men's GEL-Venture 4 Running Shoes on Sale from
$31.49 when you apply 30% Off promo code GRNMON14 (apply at checkout).
Shipping is free. |
|
t******g
发帖数: 2253 | 34 Tommy Hass，Gasquet好像也是。Asics名气还不大？四大专业跑鞋牌子，Asics, New
Balance, Brooks, Saucony，这四个中还是Asics做得最大 |
|
d*******l
发帖数: 2567 | 35 Hi, folks, I receive these kind of emails from time to time. Since I have a
job, I guess
some of you might be more interested. So take it and good luck!
Please contact the recruiter directly but if you want ask me questions, feel
free and I'll try to help.
DB
Formalized Design Inc. is looking for Six (6) Sr. ASIC VHDL Verification
Engineers for a 15 months contract position in Dallas, TX.
The ideal candidate will have strong SoC ASIC Verification experience for DSP
processors & ASIC Co- Processo |
|
e****d
发帖数: 5 | 36 Job Title: Senior ASIC Design Engineer/ Group Leader
Brief description of job duties:
路 Maintain and upgrade IC CAD tools such as (Cadence/Xlinix/Calibre
)
路 Perform IC Layout, both top level and analog layout
路 Organize design review meetings and get ready for tape out
submission
路 Interface with foundries and vendors during the design,
simulation, integration and testing of ASIC ICs
路 Provide leadership within the ASIC group and manage daily
activities |
|
h**********l
发帖数: 410 | 37 对这行还不太懂,但是感觉还是很多工作还是靠scaling维持的.过两年就16nm finfet了
,scaling真的很快就完蛋了.那ASIC还能撑多久?
大部分工作到底是怎么创造出来的?难道工艺不变的话也能有那么多design的创新来维
持ASIC这些人来打杂吗?学术界accelerator倒是炒的很热,不知道能不能成为维持数字
行业的技术.
大家觉得还能撑多久?还是跟社会有关的行业经久不衰一些,例如金融.可惜木有绿卡,英
语也不占优势... cs估计会死的晚一点,毕竟得device,asic, architecture都死了才轮
到cs.... |
|
H******d
发帖数: 98 | 38 各位前辈们好！小弟在加州系统的top3学校读ECE硕士，已毕业，主攻ASIC数字电路方
向，基本Hardware相关的技能、仪器我都会。
去年在Broadcom实习半年，做的是ASIC Design and Verification Intern，认真负责
，吃苦耐劳，上手快。
今年年初网投了几个月也没多少消息，所以恳请各位前辈内推一下ASIC相关的full
time职位，Design/Verification/Validation/Application Engineer这些都没问题，
小弟必知恩图报！
可站内联系我或者邮箱 i*******[email protected] 在此谢谢各位！ |
|
|
|
|
n**d
发帖数: 9764 | 42 某人简历
曾任美国OPTIComputer公司ASIC芯片设计经理、美国Divio公司资深ASIC设计工程师。 |
|
m**********e
发帖数: 12525 | 43 张栩
本公司副总裁兼技术研究院院长。中国科学技术大学无线电系学士学位、中国科学院空
间科学与应用研究中心硕士学位。曾任美国OPTIComputer公司ASIC芯片设计经理、美国
Divio公司资深ASIC设计工程师、NortelNetworks美国公司核心交换网络设备资深工程
师、NortelNetworks中国公司企业级网络设备研发经理、美国SupermicroComputer公司
首席工程师、浪潮信息（股票代码：000977）产品总监兼高端服务器研发部副总经理。 |
|
t******e
发帖数: 2504 | 44 ASIC, 好像指专用芯片，相对的，是CPU/GPU之类的通用芯片。
最近挖矿的ASIC芯片提的比较多。 |
|
发帖数: 1 | 45 Application Specific Integrated Circuit
是搞一种硬件出来，专门用来对某种算法计算方式进行运算。
比如高频交易，或者现在流行的挖矿，都可以用ASIC来搞
一般来说ASIC的效率是CPU/GPU成百上千倍 |
|
N*****g
发帖数: 49 | 46 小弟在加州系统的top3学校读ECE硕士，明年年初毕业，主攻ASIC数字电路方向，基本
hardware相关的技能、仪器我都会。
今年在Broadcom实习半年，做的是ASIC design and verification intern
细心，认真负责，吃苦耐劳，上手快。恳请各位前辈内推一下full time职位，小弟必
知恩图报！
可站内联系我或者邮箱:i*******[email protected] 在此谢谢各位！ |
|
H******d
发帖数: 98 | 47 各位前辈们好！小弟之前发过一次求内推帖子，在这里：
http://www.mitbbs.com/article_t0/JobHunting/32654027.html
非常感谢前辈们的推荐，拿到一家大公司和小公司的面试，最终也进入了onsite，只可
惜经验不足都挂掉了。
总结一下经验：
1. 大公司的面试时面试官要求写Asynchronous FIFO的Verilog code，这块没准备好，
挂掉。面完之后立刻把Asynchronous FIFO的Verilog从头到尾自己写了一遍，把网上所
有关于ASIC/VLSI的面经过了两遍。
2. 自信满满去小公司onsite面试，所有技术问题都答出来了，但是其中有一轮的面试
官问我简历一个2年前的proj，问得很细，其中有个细节真心不记得了，所以答得不好
挂掉。面完之后立刻把简历上所有内容重新仔仔细细地回顾一遍，当初的proj代码也重
新写了一遍。
现在仍然在找ASIC/Digital相关的工作，所以厚着脸皮继续上来寻求前辈们的推荐，相
信这次一定可以拿下！
可站内联系我或者邮箱 i*******[email protected] 在此谢谢各位！ |
|
T******T
发帖数: 3066 | 48 Interviewed in marvel on-site, loved the cafeteria, free and good food.
ASIC/Emulation related position, most of the questions are pretty industry
standard and could include some of the following topics:
ASIC design process, rtl/gate sim topics, STA, timing violation mitigation,
Async/Sync FIFO design basics, Time domain crossing techniques, Divide by
circuits, DSP Matlab modeling, low power design techniques, FPGA emulation
process & limitations. Physical design knowledge, Power integrity, ESD |
|
t*********n
发帖数: 378 | 49 东北某小学校淹没在周围无数牛校光芒里 ece fresh master 论文和project都是围绕
FPGA方面的东西 ASIC后端仅仅有本科一点点有限的认识
公司是2002年成立的小公司，一直管自己叫startup company。 以前一直做系统/PCB级
别的产品，2年前在东北设立asic分支，有20几个engineer。从学校career center找到
的招聘信息 不过是找bachelor degree的，design和verification各一个opening
提前两周HR manager电话询问了大概的兴趣 available的时间 身份，然后说有
engineer会电话来谈谈--同时建议我设置一下语音信箱因为我错过了他们的第一次电话
（汗）。
两天后engineerA电话如约而至。聊简历上的project，同时说他本人不是做某某方向
理论上的东西不一定能很快理解。但是还是尽可能的和他吹，说了大概20分钟，结束。
两天后HRemail说约时间onsite
上周五冒着大雨飞奔一个小时到公司。EngineerA是host，领着在他们office转了一圈
，介绍了下目前正 |
|
m****g
发帖数: 810 | 50 【 以下文字转载自 SanDiego 讨论区 】
发信人: maoing (SABRE), 信区: SanDiego
标 题: Graphics ASIC Verification opennings
发信站: BBS 未名空间站 (Wed Apr 14 02:43:22 2010, 美东)
Our group has several Verification opennings for Graphics (2D/3D) ASIC.
Prefer handson skills but may also consider excellent entry level candidates
. Will be exposed to Vera/System Verilog/VHDL/Verilog/OOP/RVM environment.
Required to be relocated to San Diego, CA if not local. |
|
