m****s 发帖数: 18160 | 1 【 以下文字转载自 EE 讨论区 】
发信人: sizhiyi (sizhiyi), 信区: EE
标 题: Job Opening in Broadcom ---- VLSI/Physical Design Engineer (可以内推)
发信站: BBS 未名空间站 (Sun Apr 21 16:47:59 2013, 美东)
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
RESPONSIBILITIES:
• Ownership of design floor planning, synthesis, DFT, place and
route, clock and power distribution, static timing analysis, signal
integrity analysis, physical verification.
• Use circuit design skills to verify clock and power
implementation.
• Contribute to developing physical design methodologies and RTL to
GDS flow automation.
JOB REQUIREMENTS:
• BSEE, MSEE Preferred
• 2+ years directly related physical design expertise in state of
the art ICs with emphasis on VLSI physical design and methodology on 45 and
28 nanometer process nodes.
• A solid understanding of digital circuit design and Verilog.
• Able to analyze static timing paths for high speed digital blocks
, and implement design fixes to meet block frequency target.
• Basic understanding for circuit design of custom macro blocks
such as RAMs, Register Files, CAMs, high-speed IO drivers and other IP cells
.
• Power user of place and route tools such as Atoptech, ICC, Magma
or Cadence SOCe
• Able to identify, extract and simulate critical paths using
Hspice.
• Able to create schematics from RTL for semi-custom designs.
• Strong hands on familiarity with Design Compiler, Calibre, Hspice
, LEC, Formality, Primetime SI, Redhawk and StarRC preferred.
• Proficiency using Perl, TCL.
• Able to work in a small team environment.
• Self Motivator and excellent problem solving skills. |
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