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发帖数: 102 | 1 (有意请PM!)
Job Description
The Processor Division of Broadcom Corporation is well known in the
semiconductor industry for providing super high-performance multi-core
network microprocessors. We are staffing up in critical R&D areas in the
high-rise facility at Highway 101 & Great America Parkway in Santa Clara, CA
.
As a senior system Logic Design Engineer you will be responsible for
performing micro-architecture and logic design in the development of system
logic in high performance multi-threaded, multicore CPU design. The
efficiency of caches, DRAM controller, interconnect and various on-chip
accelerators and interfaces will be key to delivering maximum performance in
the system.
This is an opportunity to broaden your chip and system view as a member of a
key-contributing group at Broadcom. The Multi-core XLP Network Processor
has been touted “An Exceptional CPU, well beyond the capabilities of other
embedded processors” by The Microprocessor Report, July 2010.
Responsibilities
• Develop micro-architecture specification for assigned system block(s)
• Implement the RTL code for the unit.
• Collaborate with verification team in the development of testplan,
testbench and tests; and assist in debugging of test failures.
• Support physical design team in writing timing constraints, analyze
timing violations and perform timing fixes in RTL.
• Own and drive future design of additional system blocks
• RAID/Compress/Decompress experience preferred
-VV1
Job Requirements
• Total engineering minimum experience required is typically a BSEE
degree and 12 years of experience, an MSEE degree and 9 years of experience
or a PhD EE and 6 years of experience or equivalent.
• Prior experience in interconnect, serial interfaces, DRAM
controllers is a big plus.
• Working knowledge of Verilog, multi-domain clock synchronization,
pipelining, various flow control methods and low-power techniques.
• Excellent written and verbal communication skills. |
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