a**w 发帖数: 267 | 1 Experienced IC designers are welcome to send me a message here. I'll forward
to HM.
Thanks!
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Auto req ID 29906BR
Job Posting Title Senior level IC Design Engineer (PCIe / Soc)*
Business Unit Mobile and Wireless Group
Job Description With a pure digital CMOS approach and excellent blocking
performance, Broadcom's chipsets and system solutions provide the technology
to make wireless networking a reality. Providing radio frequency, baseband,
system and complete software support to OEMs and system integrators,
Broadcom's chips enable the wireless sharing of data among from mobile
devices. As a senior engineering team member, you will contribute to the
design, development and verification of Broadcom's highly successful
Wireless Connectivity SOCs.
Responsibilities include: • Lead the block level architecture design &
#8226; Author detailed design documents • Develop and execute thorough
simulation and lab verification plan • Participate in the emulation
platform development and lab debugging • Participate in synthesis,
static timing analysis, DFT • Assist in the development of embedded FW
. - Location is flexible, will consider San Diego, CA and Santa Clara, CA.
J2W:LI-NH1
Job Requirements
• Typically requires a BS degree and 9+ years of experience or an MS
degree and 6+ years of experience or a PhD and 3+ years of experience is
preferable
• Good knowledge and hand-on experience on SoC chip assembly.
• Good knowledge of digital communication systems and low power, high
speed digital circuit design.
• Strong analytical, and problem solving skills as well as hands-on
lab debugging skills.
• Good knowledge of RTL design and verification.
• Good Knowledge in languages relevant to the ASIC development process
including Verilog, VHDL, Unix Scripting, and C.
• Experience with communication systems/protocols such as 802.11, PCIe
, USB3, SDIO is a plus:
• Self-motivated, excellent communication skills and ability to excel
in a team environment.
Country United States
State/Province California
City/Town San Diego
Shift 1st Shift - Day
Percent of Travel Required 5% - 10%
Function Engineering
Discipline IC Design
Alternate Location(s) US - California, Northern – Bay Area
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