f**u
发帖数: 559 | 1 The point is how do you calculate the snr? because it is tricky. it is signal
and noise.
uaually ppl forcus on the int1 noise which comes from two sides: switch noise
and opamp noise.
switch noise is kt/c, so big cap helps.
opamp noise you can run hspice and later refer all them back to your input
side.
also noise and distortion are two different issues. good settling help
distortion. big dc gain at int1 help its distortion, also help to attenuate
int2, int3 etc noise and distortion (that is the | f**u
发帖数: 559 | 2 //ft. are you doing silicon design or sth else?
the testing you are talking about is for real circuit or just simulation?
how could you calculate/simulate snr in time domain? you have to do fft and
convert to freq domain to calculate the snr.
my previous post is talking about the silicon design. as a real product,
for the cost reason, you have to let your analog circuit noise dominate the
performance. for modulater, you can easily design a high-order modulator to
get a good snr. (2nd order may n |
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