a******e
发帖数: 80 | 1 I am using CADENCE Virtuoso Analog Design Environment for simulation . The
simulator opted is AMS. Basically, I have two main blocks to be simulated.
One is written in verilog code and created as a functional view while the
other block is drawn in schematic using foundry's cells. Thus, it is a mixed
-signal simulation and AMS simulator is chosen.
When I simulated the config view of the above circuits, I got thousands of
error messages (all in the same type) in my simulation.log
ncelab: *W,DLCILI |
a*m
发帖数: 6253 | 2 copy hierarchy to new lib.
but i doubt it is capital spell problem. i use capital letter all the time,
never see an issue.
double check ur config view, it should be small mistakes. For example, the
name of lib is defined with typo. |
a******e
发帖数: 80 | 3 I reckon it is a common problem when running mixed-signal simulation. You
are lucky not to have it. Your CADENCE support people probably has taken
care of the setting.
It has something to do with the name mapping. When case-insensitive names
are mapped into a case-sensitive name space, it cause problems.
Since you don't have any difficulty running mixed-signal simulation using
AMS simulator, please could you do me a favor to check you .cshrc file
because the solution may be just there.
Do you ha
【在 a*m 的大作中提到】
: copy hierarchy to new lib.
: but i doubt it is capital spell problem. i use capital letter all the time,
: never see an issue.
: double check ur config view, it should be small mistakes. For example, the
: name of lib is defined with typo.
|
a*m
发帖数: 6253 | 4 That makes sense.
It is not in my local or project .cshrc.
Not sure which scrpt they inserted the name mapping rules.
that
contains
【在 a******e 的大作中提到】
: I reckon it is a common problem when running mixed-signal simulation. You
: are lucky not to have it. Your CADENCE support people probably has taken
: care of the setting.
: It has something to do with the name mapping. When case-insensitive names
: are mapped into a case-sensitive name space, it cause problems.
: Since you don't have any difficulty running mixed-signal simulation using
: AMS simulator, please could you do me a favor to check you .cshrc file
: because the solution may be just there.
: Do you ha
|
a*m
发帖数: 6253 | 5 BTW, what version of AMS simulator you are using?
The new one should fix a lot of bugs like this.
Of coz, it creates a lot of new bugs as well, :-) |
a******e
发帖数: 80 | 6 My ADE invoked ncsim 06.11-s002 for simulation.What did you use?
We contacted cadence regarding the problem and were told to surpress the
warning message.So the warning messages become invisible. But it is not a
solution, is it? |
ET
发帖数: 10701 | 7 为啥不是solution? cadence自己还没解决这些warning问题。
有些公司自己开发的technology realted toolkit, 也是成堆成堆的warning..
【在 a******e 的大作中提到】
: My ADE invoked ncsim 06.11-s002 for simulation.What did you use?
: We contacted cadence regarding the problem and were told to surpress the
: warning message.So the warning messages become invisible. But it is not a
: solution, is it?
|
a******e
发帖数: 80 | 8 could be.
But cadence is not cadence without critics like us (sometimes quibbler) :) |
