a******e
发帖数: 80 | 1 代朋友问个问题，谢谢。
“I have a delay circuit built with 9 cascade inverters. The schematic
of this circuit was created in Cadence Virtuoso, then the netlist was
extracted and imported to SoC Encounter for layout. The problem is
that Encounter automatically eliminated 8 inverters from the circuit.
The question is: how to set Encounter to layout the circuit as it is?
Many thanks!” |
a******e
发帖数: 80 | 2 Come on guys. There must be some experts on SoC Encounter on this forum.
I assume it is our fault to get zero reply. Maybe the question was not very
clear. I am providing more details in this post and hope you guys can make
some comments and continue the thread.
What we are trying to do is to convert our custom digital schematic into a
layout. The digital schematic is made of standard digital gates only. At the
moment, my colleague and I had difficulty getting a layout matched to our
schematic. |
ET
发帖数: 10701 | 3 去edaboard.com去问吧。
very
the
【在 a******e 的大作中提到】
: Come on guys. There must be some experts on SoC Encounter on this forum.
: I assume it is our fault to get zero reply. Maybe the question was not very
: clear. I am providing more details in this post and hope you guys can make
: some comments and continue the thread.
: What we are trying to do is to convert our custom digital schematic into a
: layout. The digital schematic is made of standard digital gates only. At the
: moment, my colleague and I had difficulty getting a layout matched to our
: schematic.
|
a******e
发帖数: 331 | 4 I am not a SOC encounter expert and using Synopsys.
I think SOC Encounter same as other Place & Routing tools, based on
constraints to determine the buffer stages and driving strength. In Design
Compiler, you can set dont touch on the netlist and buffers to keep the
netlists. You can find equivalent command in SOC encounter.
very
the
【在 a******e 的大作中提到】
: Come on guys. There must be some experts on SoC Encounter on this forum.
: I assume it is our fault to get zero reply. Maybe the question was not very
: clear. I am providing more details in this post and hope you guys can make
: some comments and continue the thread.
: What we are trying to do is to convert our custom digital schematic into a
: layout. The digital schematic is made of standard digital gates only. At the
: moment, my colleague and I had difficulty getting a layout matched to our
: schematic.
|
m**********e
发帖数: 57 | 5 I remember that there is an option: do not restructure logic(or similar name
) when you optimize the design. Search SoCE manual, or you can have this
simple question answered with cadence sourcelink. Sorry can not give you
answer, I am away from IC design for 3 years. |
