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发帖数: 84 | 1 工作地点：Newport Beach, California.
Job Description and Responsibilities:
" DRC/LVS and extraction verification support for SOC and Analog Mixed
Signal Designs
" Write and implement custom DRC/LVS and extraction rules
" Maintain and update physical verification tools and foundry rule
decks
" Support tapeout tasks, assist layout engineers in understanding and
fixing layout errors, run DFM and CMP/Yield Enhancement scripts if
needed.
" Integrate new foundry rules into existing verification flow
" Verification tool license management
" IC Package extraction and SI analysis (optional)
Required Skills and Experiences
" M.S. in EE and 3 yrs experience or B.S. in EE and a minimum 5 yrs
experience as a layout physical verification engineer
" Experienced with layout and verification tools (Cadence Virtuoso
design environment, Mentor Calibre and Synopsys StarRC)
" Experienced with Perl, TVF and tcl scripting
" Experience in create P&R techfiles
" Experienced in debug and fix physical layout design issues
" Experience with rule file coding (DRC/LVS/XRC)
" Familiar with UNIX/LINUX operating systems
" Experience with Ansoft HFSS, Q3D and SIwave (optional)
" Cadence APD/Allegro (optional)
" Spice Simulation (optional) |
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