s***m 发帖数: 336 | 1 几天前面试题,不太明白。请教大家。
1. 一个PLL生成的clock signal,有两条支路,一条支路通过3个buffer连接着一个
Flip-flop,另一个支路通过5个buffer连接着一个Flip-flop。这两条支路的delay是相等的。
问:哪条支路的click jitter更严重?
我不太有思路,应该从什么角度分析呢?谢谢。
2. PMOS和NMOS,哪个的leakage current 更严重?
3. 一个drive通过一根连线连接着一个receiver,在drive端和receiver端各有一个电
容Cc(和其他导线之间的寄生电容)。如果我可以remove掉一个其中一个Cc,remove掉哪一个比
较好?
我想是不是应该移掉靠近receiver的那个,因为它引起的delay比较大? |
I***a 发帖数: 704 | 2 面试怎么都问这些边角余料的问题,还是你隐瞒了你会的问题?
1. 5个buffer那个。
2. pmos
3. receiver端 |
m******e 发帖数: 106 | 3
相等的。
i guess 5, more chance to have temporal variations
both off? definitely NMOS
掉哪一个比
receiver end due to noise coupling issues
【在 s***m 的大作中提到】 : 几天前面试题,不太明白。请教大家。 : 1. 一个PLL生成的clock signal,有两条支路,一条支路通过3个buffer连接着一个 : Flip-flop,另一个支路通过5个buffer连接着一个Flip-flop。这两条支路的delay是相等的。 : 问:哪条支路的click jitter更严重? : 我不太有思路,应该从什么角度分析呢?谢谢。 : 2. PMOS和NMOS,哪个的leakage current 更严重? : 3. 一个drive通过一根连线连接着一个receiver,在drive端和receiver端各有一个电 : 容Cc(和其他导线之间的寄生电容)。如果我可以remove掉一个其中一个Cc,remove掉哪一个比 : 较好? : 我想是不是应该移掉靠近receiver的那个,因为它引起的delay比较大?
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I***a 发帖数: 704 | 4 2. pmos more leakage
in subthreshold region, pmos more current,
in triode and saturation region, nmos more current.
【在 m******e 的大作中提到】 : : 相等的。 : i guess 5, more chance to have temporal variations : both off? definitely NMOS : 掉哪一个比 : receiver end due to noise coupling issues
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s***m 发帖数: 336 | 5
谢谢。
其他问题都很基本,比如时钟周期和setup time的关系。hold time的关系什么的。还
有画2输入
NAND gate,做些分析。
【在 I***a 的大作中提到】 : 面试怎么都问这些边角余料的问题,还是你隐瞒了你会的问题? : 1. 5个buffer那个。 : 2. pmos : 3. receiver端
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s***m 发帖数: 336 | 6
怎么解释5个buffer那条支路有更多的jitter?
第3问怎么能不能解释下?
多谢!
【在 I***a 的大作中提到】 : 面试怎么都问这些边角余料的问题,还是你隐瞒了你会的问题? : 1. 5个buffer那个。 : 2. pmos : 3. receiver端
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I***a 发帖数: 704 | 7 1, 3问 我瞎猜的,
【在 s***m 的大作中提到】 : : 怎么解释5个buffer那条支路有更多的jitter? : 第3问怎么能不能解释下? : 多谢!
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g******u 发帖数: 3060 | 8 third answer:
why remove the receiver end cap? it should form a low pass as seen by the
drive side, only will be beneficial.
I guessed. |
s**g 发帖数: 66 | 9 I guess the answer to Q1 shall be:
3 stage buffer approach leads to more jitter
Here is my reasoning:
single stage buffer jitter can be defined by
jtter_single = vn / slope
where vn is buffer input referred noise (assume the same in both cases),
slope is input signal rising/falling edge slope
since jitter from each stage is uncorrelated, we have
jitter_total = sqrt( N * (jitter_single)^2 )
where N is number of buffer stages
If we assume in both cases, buffer signal swing are the same Vswing and trip
point is at the middle, it's easy to find
slope = Vswing / 2 / (Delay/N)
where Delay is total delay
Therefore we have
jitter_total proportional to sqrt(1/N) when delay is fixed
This has physical implication:
you'd rather have fast multiple stage buffer than slow but fewer stage
buffer. |
s**g 发帖数: 66 | 10 Q3: remove rx side cap
you listed one reason: line + cap would have filter effect
I like to push the envelope:
driver normally handles its immediate load better, e.g. linear driver with
voltage mode feedback. Load cap at TX side won't affect output waveform by
much. However, receiver side cap causes delay/ISI/filtering, which can't be
corrected by TX side feedback and thus shall be avoided.
Similar effect can be found in CML/ECL logics. |
g******u 发帖数: 3060 | 11 it's interesting.
Based on same reason we got different answers. It'll depend then, sometimes
filtering is better for protection/cancelling noise, but other times you
wanna avoid it as it causes delay.
be
【在 s**g 的大作中提到】 : Q3: remove rx side cap : you listed one reason: line + cap would have filter effect : I like to push the envelope: : driver normally handles its immediate load better, e.g. linear driver with : voltage mode feedback. Load cap at TX side won't affect output waveform by : much. However, receiver side cap causes delay/ISI/filtering, which can't be : corrected by TX side feedback and thus shall be avoided. : Similar effect can be found in CML/ECL logics.
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x*******i 发帖数: 57 | 12 for 3, I think it's better to remove receiver side cap.
Driver output is usually low impedance while receiver input is usually
high impedance. That means driver output is less sensitive to parasitic
cap.
to make it more clear, consider 3 cases:
(1) no cap at both sides (this should be ideal situation)
(2) cap at driver side only
(3) cap at receiver side only
(2) is more close to the ideal situation than (3) is, because the cap
won't affect the driver output much.
相等
的。
掉哪一个
比
【在 s***m 的大作中提到】 : 几天前面试题,不太明白。请教大家。 : 1. 一个PLL生成的clock signal,有两条支路,一条支路通过3个buffer连接着一个 : Flip-flop,另一个支路通过5个buffer连接着一个Flip-flop。这两条支路的delay是相等的。 : 问:哪条支路的click jitter更严重? : 我不太有思路,应该从什么角度分析呢?谢谢。 : 2. PMOS和NMOS,哪个的leakage current 更严重? : 3. 一个drive通过一根连线连接着一个receiver,在drive端和receiver端各有一个电 : 容Cc(和其他导线之间的寄生电容)。如果我可以remove掉一个其中一个Cc,remove掉哪一个比 : 较好? : 我想是不是应该移掉靠近receiver的那个,因为它引起的delay比较大?
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s***m 发帖数: 336 | 13 今天去问了下老师,得到一些答案:
1)3个buffer那条支路的jitter更严重。因为jitter的来源是manufacture,
temperature, voltage variations, jitter可正可负,buffer越多,各个buffer所带
来的jitter可能会相互cancel off。所以,5个buffer的支路比3个的支路的jitter要少。
2)NMOS比PMOS的leakage current要严重。因为nmos的threshold voltage低。
3)老师 也不太明白。
仅供参考。欢迎发表更多见解!谢谢。 |
g******z 发帖数: 495 | 14 第一个答案好怪啊。
能不能理解为3个/5个相同的噪声源叠加?
少。
【在 s***m 的大作中提到】 : 今天去问了下老师,得到一些答案: : 1)3个buffer那条支路的jitter更严重。因为jitter的来源是manufacture, : temperature, voltage variations, jitter可正可负,buffer越多,各个buffer所带 : 来的jitter可能会相互cancel off。所以,5个buffer的支路比3个的支路的jitter要少。 : 2)NMOS比PMOS的leakage current要严重。因为nmos的threshold voltage低。 : 3)老师 也不太明白。 : 仅供参考。欢迎发表更多见解!谢谢。
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