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JobHunting版 - ASIC DFT engineer position for fresh graduate
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Sr. DFT Engineer position (inbox me if interested)job opening - Analog Test Engineer (转载)
相关话题的讨论汇总
话题: phd话题: dft话题: asic话题: graduate话题: fresh
进入JobHunting版参与讨论
1 (共1页)
S***l
发帖数: 383
1
my department has one opening for fresh graduate (PhD preferred) in the area
of ASIC DFT (Design for Test).
========================================================
Requirements:
- MS/PHD thesis on test related topics
- clear understanding of key VLSI test topics, such as scan, ATPG,
compression technologies
- programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
Job location is San Jose, CA. Inbox me for details if you are interested.
Need to fill ASAP.
z********1
发帖数: 262
2
已经站内信

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
3
still open.
Open for fresh graduate, PhD preferred.

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
4
still open.
for fresh graduate (planned graduation this summer/fall), PhD preferred.

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
5
my department has one opening for fresh graduate (PhD preferred) in the area
of ASIC DFT (Design for Test).
========================================================
Requirements:
- MS/PHD thesis on test related topics
- clear understanding of key VLSI test topics, such as scan, ATPG,
compression technologies
- programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
Job location is San Jose, CA. Inbox me for details if you are interested.
Need to fill ASAP.
z********1
发帖数: 262
6
已经站内信

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
7
still open.
Open for fresh graduate, PhD preferred.

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
8
still open.
for fresh graduate (planned graduation this summer/fall), PhD preferred.

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

S***l
发帖数: 383
9
still open.
for fresh graduate (planned graduation this summer/fall), PhD preferred.

area

【在 S***l 的大作中提到】
: my department has one opening for fresh graduate (PhD preferred) in the area
: of ASIC DFT (Design for Test).
: ========================================================
: Requirements:
: - MS/PHD thesis on test related topics
: - clear understanding of key VLSI test topics, such as scan, ATPG,
: compression technologies
: - programming skills: Verilog/VHDL, Unix scripting(tcl, perl, shell)
: Job location is San Jose, CA. Inbox me for details if you are interested.
: Need to fill ASAP.

1 (共1页)
进入JobHunting版参与讨论
相关主题
job opening - Analog Test Engineer (转载)招人 - two positions
一个猎头发来的机会EDA 公司在Austin office的一个支持工程师职位 (转载)
Job opening求ASIC design/verification的refer
找cs码工工作的话简历里写会verilogSr. DFT Engineer position (inbox me if interested)
multiple openings in ASIC design(Santa Clara) (转载)恳求工作内推: Electrical and Computer Engineering方向
最后一次恳求工作推荐: EE--------Digital Logic Design/VLSI/恳求工作内推: Electrical and Computer Engineering方向
Verilog问题恳求工作内推: Electrical and Computer Engineering方向
请教amd的面试怎么准备[Campbell, CA] Hiring Sr. Physical Design Engineer
相关话题的讨论汇总
话题: phd话题: dft话题: asic话题: graduate话题: fresh