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发帖数: 93 | 1 Location: Sr. Design Engineer – MRAM, directly report to the Director of
Product Development.
Company: Pre IPO
Qualification:
MSEE or PHDEE
3-8 yrs experience
CMOS memory design, esp. MRAM, DRAM, FLASH, SRAM
High-speed IO, DDR2/3 background, CAD experience are highly desired
Contact:
Hui Shen
h*****************[email protected]
h*[email protected]
Feel free to contact me if you are interested positions of
Power Management IC Designer: Bay
Mixed Signal Design Engineer: Bay
Analog Design Director: |
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