m********u
发帖数: 3942 | 1 Location: San Jose, California
Responsibilities:
Work closely with FPGA design team to review and understand specifications /
architectures / micro-architectures
Work closely with software team to define API, develop driver code and FW
code
Build infrastructure for functional/performance validation, NAND
characterization and manufacturing test
Define test plans to cover FPGA design / drivers / NAND features.
Develop and execute test cases to validate new hardware features at module/
chip/systems level
Run regression and debug / triage failures in validation environment and
reproduce issues in simulation environment
Support field failure analysis and system level performance evaluation.
Requirements:
BSEE with 5+ years or MSEE with 3+ years experiences
Good knowledge of standard ASIC/FPGA design/verification/post silicon
validation flows
Experience with C/C++ and Python scripts
Knowledge of industry high speed interface standard protocols (PCI Express,
DDR, NAND Flash etc.) strongly desired
Experience in computer storage and networking is desired
Should be a team player with excellent communication skills and the desire
to take on diverse challenges
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