D**0
发帖数: 2048 | 1 发信人: forreal (really), 信区: SanFrancisco
标 题: 【JOBS】招Java Developer/QA若干
发信站: BBS 未名空间站 (Mon Oct 18 18:00:41 2010, 美东)
我们公司San Jose office有一些Java Developer和QA的openings。主要是中级的
positions （3-5年经验吧），QA有两个比较entry level的。另外还有一个build/
release engineer。
有兴趣的话PM给我email地址，我会给你发具体信息。
================分割线================ | G*S
发帖数: 831 | 2 最近弯曲好多job opening 啊~~~
【在 D**0 的大作中提到】
: 发信人: forreal (really), 信区: SanFrancisco
: 标 题: 【JOBS】招Java Developer/QA若干
: 发信站: BBS 未名空间站 (Mon Oct 18 18:00:41 2010, 美东)
: 我们公司San Jose office有一些Java Developer和QA的openings。主要是中级的
: positions （3-5年经验吧），QA有两个比较entry level的。另外还有一个build/
: release engineer。
: 有兴趣的话PM给我email地址，我会给你发具体信息。
: ================分割线================
| D**0
发帖数: 2048 | 3 发信人: notears (三七开), 信区: SanFrancisco
标 题: 【JOBS】招聘Full Time Warehouse Manager
关键字: warehouse manager,job
发信站: BBS 未名空间站 (Tue Dec 7 19:04:53 2010, 美东)
我公司系一家电子商务公司。因业务扩张迅速，现聘请全职 Warehouse and logistics
manager 一名。 具体要求是：
* Familiar with shipping carriers, USPS, Fedex, UPS, DHL and mail classes.
* Good organization management skills.
* Fluent in English and Mandarin.
* Comfortable with multi-task working environment.
* Undergraduate degree with 2-3 years relevant experience is a plus.
* Legal to work in the US (no H1B support).
Location: east bay area.
有意者请将简历 发至 j*******[email protected]. 谢谢关注。 | D**0
发帖数: 2048 | 4 发信人: azurelan (azure), 信区: SanFrancisco
标 题: 【JOBS】NCG CAD Engineer
发信站: BBS 未名空间站 (Mon Dec 6 20:07:46 2010, 美东)
In this position, the individual will be responsible for developing/
supporting physical verification rule decks (LVS/DRC/ERC) for the layout
group, completing placement and routing flow/methodology development,
developing/supporting/calibrating parasitic extraction flow for design
groups, developing the CAD flow for memory design as per the layout and
designing requirements and improving overall productivity for layout group
through various scripts and SKILL programming. The individual will also
develop and apply computer aided design (CAD) software engineering methods,
theories and research techniques in the investigation and solution of
technical problems, assess architecture and hardware limitations, plan
technical projects in the design and development of CAD software, define and
select new approaches and implementation of CAD software engineering
applications and design specifications and parameters and develop routines
and utility programs. Lastly the individual will prepare design
specifications, analysis and recommendations for presentation and approval
and may specify materials, equipment and supplies required for completion of
projects and may evaluate vendor capabilities to provide required products
or services.
This position requires experience in CAD Development and
Support, experience in flow/methodology development for Custom IC Design,
solid programming experience in PERL and DFII SKILL, demonstrated experience
in developing/customizing/enhancing foundry physical verification rule
decks for DRC/LVS/ERC applications, experience in defining and improving
place and route flow, experience with parasitic RC extraction flow
development and user support, experience in tool maintenance and interface
with tool vendors, working experience with global multi-site teams in a
development/support role and must have excellent communication skills. The
individual must also have experience with Calibre or Hercules or Assura,
experience supporting Cadence custom IC design tools: VCP/CCAR/CSR and be
proficient with DFII SKILL, PERL, experience with StarRCXT/Calibre xRC/
Quickcap is preferred. | D**0
发帖数: 2048 | 5 发信人: JLo (JLo), 信区: SanFrancisco
标 题: [Jobs] San Jose EECS major Engineer and PM positions
发信站: BBS 未名空间站 (Fri Dec 3 14:00:33 2010, 美东)
Our company is hiring 4 senior level engineers:
1. High priority: Senior engineer with knowledge and experience in storage
servers.
2 . High priority: Senior engineer with knowledge and experience in GPU.
3. Senior engineer with knowledge and experience in blade servers.
4. Low priority: Senior engineer with knowledge and experience in server
BIOS and firmware.
Entrance level engineer positions available too.
Thanks. | D**0
发帖数: 2048 | 6 This thread will be un-pinned
【在 D**0 的大作中提到】
: 发信人: JLo (JLo), 信区: SanFrancisco
: 标 题: [Jobs] San Jose EECS major Engineer and PM positions
: 发信站: BBS 未名空间站 (Fri Dec 3 14:00:33 2010, 美东)
: Our company is hiring 4 senior level engineers:
: 1. High priority: Senior engineer with knowledge and experience in storage
: servers.
: 2 . High priority: Senior engineer with knowledge and experience in GPU.
: 3. Senior engineer with knowledge and experience in blade servers.
: 4. Low priority: Senior engineer with knowledge and experience in server
: BIOS and firmware.
| D**0
发帖数: 2048 | 7 please follow the new post |
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