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l********g
发帖数: 68 | 1 借用朋友的帐号发帖。
组里最近有openning.感兴趣的请站内回信。
Job Posting Title IRC97918
Job Title Senior Design Engineer
Detailed Description
Xilinx is looking for a highly qualified IC design engineer to join
the clocking hardware design team. This individual will work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. The engineer will be involved in the entire design
process including RTL design, schematic generation, layout guidance, timing
and electrical verification, and working with test engineers on silicon
verification and characterization.
Job Requirements
• BS or MS in Electrical Engineering
• 2 plus years of industry experience in mixed signal or high speed
digital design
• Skilled in full custom or structured custom design and
verification
• Experience with static timing analysis tools a plus
• Working knowledge of scripting languages such as Perl
• The ideal candidate will also be familiar with mixed signal
blocks such as PLLs and DLLs
• Good communication skills – ability to write test plans, conduct
peer reviews and work well in a multisite team |
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