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| ● Job opening: Analog/Mixed-Signal IC Design Engineer | ● 女生求助，Hardware New Grads 想找这里的哥哥姐姐推荐，或是出出主意，聊聊经验 | | ● Xilinx openning | ● Job open in Intel Folsom, CA: Senior System Validation Engineer | | ● EE Applications Engineer Position in Southern California | ● multiple Job opens in system validation team Intel Folsom, CA: | | ● 【工作机会】SERDES system architect in Silicon Valley | ● multiple Job opens in system validation team Intel Folsom, CA | | ● Hiring Experienced Logic Designers (Nvidia) | ● [Cupertino] 内部推荐机会，苹果DDR PHY组 (转载) | | ● 面试建议加祝福 | ● Mixed Signal Design Engineer Opening in SINGAPORE | | ● Opening: Senior Analog/Mixed-Signal designer | ● [Apple Jobs] Silicon Engineering - CAD,VLSI, IP, etc | | ● [Apple Openings] software, silicon, graphic, ISP, ASIC, RF | ● Job Opening: Broadcom, Irvine, SerDes (转载) |
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n*********h
发帖数: 98 | 1 *********************************************
代友转发，请勿回信箱，直接发信给联系人邮件。谢谢！
*********************************************
We are a fast-growing company located in Silicon Valley,
and currently have a few job openings on high-speed SerDes design as
following; please feel free to send your resume to
[email protected]
/* */ if interested.
-> Job opening 1: Analog/Mixed-Signal IC Design Engineer
Ideal candidates should have previous circuit-design experiences in at
least one of the following: CDR, PLL/DLL, (wireline) transmitter, data
converter; all levels of experiences are welcome. Minimum five years
of experience in analog design is required.
-> Job opening 2: Digital RTL Design Engineer
Ideal candidates should have previous design experiences in RTL design
and verification for high-speed SerDes PHY (10Gbps and above). Minimum
five years of experience in high-speed digital front-end design is required. | i*****h
发帖数: 1534 | |
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