l******o
发帖数: 90 | 1 This is a analog IC design manager position available in Shanghai from a
NASDAQ listed company. You will manage a local team and has very
competitive compensation.
Requirements: MS plus 8 years or Ph.D plus 5 years design experiences with
wireline or RF circuits in multiple generations of CMOS process, such as
65nm, 40nm and 28nm. Project lead experiences must, manager experiences
preferred.
If interested, please contact me. Thanks. |
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