n*****a
发帖数: 313 | 1 有一个很简单的问题，苦苦思索没有好的办法，各位大侠指点。
问题：关于集成电路设计的，有一个sample信号的电路，对于sample到的模拟电压（DC
），想保持比较长的时间，例如几秒或者更长。如果用一个电容保存的话，随着时间推
进，由于漏电流会使电容的电压逐渐降低，这样时间比较长的话，所要保持的信号就衰
减了。请教有没有一个电路结构能够自动的补偿漏电流的影响？
非常感谢。 |
s***f
发帖数: 226 | 2 典型的dynamic circuit的load floating问题，加个pmos header，output加个inv，
inv的output连到pmos，那么就能自动charge回来了。
如果我没有理解错楼主的意思的话。 |
h********t
发帖数: 555 | 3 For me, this is not a simple question.
You have to either improve the process and layout to reduce the leakage, or
convert it to digital with ADC and store it in registers, than convert it
back to analog signal with DAC when you need it.
I would love to know who has a better solution. |
h********t
发帖数: 555 | 4 The signal he talked about is analog..
【在 s***f 的大作中提到】
: 典型的dynamic circuit的load floating问题，加个pmos header，output加个inv，
: inv的output连到pmos，那么就能自动charge回来了。
: 如果我没有理解错楼主的意思的话。
|
s***f
发帖数: 226 | 5 看漏了"模拟"两字，只做digital的飘过。
【在 h********t 的大作中提到】
: The signal he talked about is analog..
|
h********t
发帖数: 555 | 6 no problem. you are welcome to float back if you have a better idea.
【在 s***f 的大作中提到】
: 看漏了"模拟"两字，只做digital的飘过。
|
c*******l
发帖数: 4801 | 7 还有个科学实验的办法：
用个时间counter,先calibrate漏电速率，然后反推回去
多烂啊
or
【在 h********t 的大作中提到】
: For me, this is not a simple question.
: You have to either improve the process and layout to reduce the leakage, or
: convert it to digital with ADC and store it in registers, than convert it
: back to analog signal with DAC when you need it.
: I would love to know who has a better solution.
|
h********t
发帖数: 555 | 8 The leakage current could be non-linearly depending on the voltage across the capacitor. It could keep changing with time as the voltage across the capacitor changes with time due to leakage current. The leakage also changes dramatically when ambient temperature changes. If you want to calibrate it, you have to repeat this calibration process from time to time to take care such temperature drift effect. It is quite complicated.
【在 c*******l 的大作中提到】
: 还有个科学实验的办法：
: 用个时间counter,先calibrate漏电速率，然后反推回去
: 多烂啊
:
: or
|
s***f
发帖数: 226 | 9 虽然不是做模电的，但是我在想可以用feedback来实现(控制理论)。用一个op amp当
comparator，问题是ref voltage从哪儿来（这个没想明白）。至于如何recharge，这
个和数电一样，即feedback的输出控制一个header pmos。 |
n*****a
发帖数: 313 | 10 A good point! That is what I am considering now. But I still can not have a
mature schematic to realize it.
【在 s***f 的大作中提到】
: 虽然不是做模电的，但是我在想可以用feedback来实现(控制理论)。用一个op amp当
: comparator，问题是ref voltage从哪儿来（这个没想明白）。至于如何recharge，这
: 个和数电一样，即feedback的输出控制一个header pmos。
|
|
|
g****t
发帖数: 31659 | 11 有所谓的delay phase lock loop,就是你说的类似吧,不过那是数字的.
虽然不是做模电的，但是我在想可以用feedback来实现(控制理论)。用一个op amp当
comparator，问题是ref voltage从哪儿来（这个没想明白）。至于如何recharge，这
个和数电一样，即feedback的输出控制一个header pmos。
【在 s***f 的大作中提到】
: 虽然不是做模电的，但是我在想可以用feedback来实现(控制理论)。用一个op amp当
: comparator，问题是ref voltage从哪儿来（这个没想明白）。至于如何recharge，这
: 个和数电一样，即feedback的输出控制一个header pmos。
|
g****t
发帖数: 31659 | 12 RC filter能行吗?
or
【在 h********t 的大作中提到】
: For me, this is not a simple question.
: You have to either improve the process and layout to reduce the leakage, or
: convert it to digital with ADC and store it in registers, than convert it
: back to analog signal with DAC when you need it.
: I would love to know who has a better solution.
|
i******n
发帖数: 15 | 13 First you sample, then you hold. it's just a sample and hold circuit.
You can hold the charge in a floating cap, if there's no small resistance to
leak the charge, how could you lose the charge in just a few seconds?
a floating gate in an EPROM can hold the charges for 10 years, why do you
worry about just a few seconds? |
h********t
发帖数: 555 | 14 the leakage is primarily due to sampling switches, not the silicon oxide between the capacitor top plate and bottom plate.Most CMOS processes are junction isolated. If you draw a structure of such MOSFET, you will see reverse biased PN junction associated with the MOSFET. The reverse biased PN junction has leakage current, which is exponentially increases with temperature.Even if you use a silicon-oxide isolated process, there is still some leakage current through the channel. The charge migh
【在 i******n 的大作中提到】
: First you sample, then you hold. it's just a sample and hold circuit.
: You can hold the charge in a floating cap, if there's no small resistance to
: leak the charge, how could you lose the charge in just a few seconds?
: a floating gate in an EPROM can hold the charges for 10 years, why do you
: worry about just a few seconds?
|
g****t
发帖数: 31659 | 15 刚才翻了翻书。发现这个问题确实不简单。
hold circuit一般处理的都是比较短时间的hold,
leakage造成的drop的处理已经很复杂。
他原问题要求的hold时间，肯定比一般的
zero order hold之类东西里面的hold时间长不少。
所以我想，最佳方案可能还就是A/D然后把数字存起来。
the leakage is primarily due to sampling switches, not the silicon oxide
between the capacitor top plate and bottom plate.Most CMOS processes are
junction isolated. If you draw a structure of such MOSFET, you will see
reverse biased PN junction associated with the MOSFET. The reverse biased PN
junction has leakage current, which is exponent
【在 h********t 的大作中提到】
: the leakage is primarily due to sampling switches, not the silicon oxide between the capacitor top plate and bottom plate.Most CMOS processes are junction isolated. If you draw a structure of such MOSFET, you will see reverse biased PN junction associated with the MOSFET. The reverse biased PN junction has leakage current, which is exponentially increases with temperature.Even if you use a silicon-oxide isolated process, there is still some leakage current through the channel. The charge migh
|
i******n
发帖数: 15 | 16 let's say you've got a poor leaking switch with just 200K ohm Roff,
why can't you put 1000 such switch in series, then you get a 200M Roff
switch and you won't have to worry about leakage any more?
OP didn't say if how much die area he can afford to get the job done. |
h********t
发帖数: 555 | 17 He does not mention about the die size, that doesn't mean he doesn't care
about die size and cost. why don't you just run some simulation or at least
do some math before you argue? assuming the sampling cap is 10pF. That takes
a significant amount die area. also assuming the channel resistance is 100G
Ohm. is that even much larger than what you proposed of 200Meg Ohm? with
100G Ohm and 10pF, do you math, tell me what is the time constant. if
initially sampled input is 1v, and after that the ana |
c*******l
发帖数: 4801 | 18 听着不现实
【在 i******n 的大作中提到】
: let's say you've got a poor leaking switch with just 200K ohm Roff,
: why can't you put 1000 such switch in series, then you get a 200M Roff
: switch and you won't have to worry about leakage any more?
: OP didn't say if how much die area he can afford to get the job done.
|
i******n
发帖数: 15 | 19 Wow, I had to admit i didn't do any calculation. Nice explanation.
So, it turns out, it's not an easy question although it looks simple.
May call it "non-volatile analog memory". If anyone can come up with a
solution without going digital, it could be a big deal.
takes a significant amount die area. Also assume the channel resistance is
100G Ohm. is that even much larger than what you proposed of 200Meg Ohm?
with 100G Ohm and 10pF, the time constant = RC=1. if initially the voltage
on the samp
【在 h********t 的大作中提到】
: He does not mention about the die size, that doesn't mean he doesn't care
: about die size and cost. why don't you just run some simulation or at least
: do some math before you argue? assuming the sampling cap is 10pF. That takes
: a significant amount die area. also assuming the channel resistance is 100G
: Ohm. is that even much larger than what you proposed of 200Meg Ohm? with
: 100G Ohm and 10pF, do you math, tell me what is the time constant. if
: initially sampled input is 1v, and after that the ana
|
