p*********8
发帖数: 957 | 1 找ASIC的POSITION 学校学过VLSI的课 EDA的TOOL用过一些 很久没看了 想问下哪些方
面的基础知识需要看下 请大侠们帮下面 谢谢了 ~~~ | T******T
发帖数: 3066 | 2 俺帮人以前写的，差不多：
1) Verilog/VHDL, synthesizable coding style, common mistakes.
2) Design questions : clk div/N(odd), FSM, Async FIFO, Clock domain
crossing techniques, AMBA architecture, setup/hold timing related, maybe
some DSP questions.
3) Verification methodology, from design spec->requirements, testbench setup
, SystemVerilog/Vera/SystemC, assertion, code coverage, fsm coverage,
formal verif, lint, cdc, unit level sim vs system level sim. Randomization,
BIST techniques for memory, different p | p*********8
发帖数: 957 | | T******T
发帖数: 3066 | 4 如果是面比较back-end的位置，别忘了多准备一些synthesis和static timing
analysis 相关
的知识. Ex:
STA: setting up proper constraints, false path/multi-path identification,
clock tree synthesis flows, load balancing etc.
Synthesis: Basic Flow, Common synthesis errors, critical warnings to watch
out for etc.
DFT: At speed testing techniques, MBIST techniques, Logic-BIST vs Inserted
Scan, Common device level failure modes for flops vs Memory.
【在 p*********8 的大作中提到】
: 写的很全 好多不懂 哈哈
: 非常感谢~~~
| p*********8
发帖数: 957 | 5 I want to send you a message, but I cant....... | T******T
发帖数: 3066 | 6 wassup ? email's open now.
【在 p*********8 的大作中提到】
: I want to send you a message, but I cant.......
| p*********8
发帖数: 957 | 7 hehe it is closed again... | T******T
发帖数: 3066 | 8 what ? no...hold on, let me see what's going on....
no problem ah, other people mailed me already, wide open.
【在 p*********8 的大作中提到】
: hehe it is closed again...
| p*********8
发帖数: 957 | 9 it doesnt work for me though, hehe, but nothing important...it 's fine
Thanks for your information |
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