a*****8
发帖数: 261 | 1 大家说说哪个好呢？
感觉西海岸用Verilog, 东海岸用VHDL...
ASIC 都用verilog。。。 |
I***a
发帖数: 704 | 2 verilog根本不好用，如果是人工编码的话，和VHDL相比没有任何优势，
如果是synthesized netlist, 用verilog表示的话，文件比VHDL小，
仅此而已。 |
T******T
发帖数: 3066 | 3 private sector : mostly verilog, some system-verilog
Public sector/defense/academic: mostly VHDL
Verilog
pro: Much less verbose, more flexible test benching capability.
con: Less strict, more error prone, easier to have synthesis issues.
VHDL
pro: Very strict, less error prone, less headache due to code quality.
con: Much more verbose than verilog (personaly experience is about 15-
20% more lines of code) when describing the same
circuitry, less flexible test benching capability.
Most of the big U.S IC companies are verilog only, with certain IPs
integrated in VHDL. Testbench and BFM modeling are done either in verilog,
Vera, System-verilog or System-C or a combination of them. Anyone trying to
bring up a complex SOC verification environment in VHDL just got too much
time on his hands. |
e****y
发帖数: 27 | 4 这个问题讨论的多少年了，实际上总结成一两句话. VHDL是DOD给它的contractor规定的语言，想
和它做生意就要用VHDL. 这就是VHDL存在的唯一理由。除此之外，你就用verilog吧。 |
T******T
发帖数: 3066 | 5 It really also depends on the very 1st HDL language an engineer gets exposed
to, it usually sticks.
定的语言，想
【在 e****y 的大作中提到】
: 这个问题讨论的多少年了，实际上总结成一两句话. VHDL是DOD给它的contractor规定的语言，想
: 和它做生意就要用VHDL. 这就是VHDL存在的唯一理由。除此之外，你就用verilog吧。
|
a*****u
发帖数: 157 | 6 第一个HDL语言学的是VHDL，做FPGA。后来学ASIC时候才改用的VERILOG。但用VERILOG
之后就再没有写过一次VHDL。没可比性，做RTL肯定是VERILOG好使。
ARCHITECTURE LEVEL的MODELING & SIMULATION，我使着觉得SystemC还是比较方便的。
不过其实最好是这些都学一下，至于到底用什么，大多是取决你周围的工作环境。 |
O*y
发帖数: 317 | |
O*y
发帖数: 317 | 8 我下了个Altera 6.5, 看书，( Verilog HDL--Guide to Digital Design & Synthesis
), 自己写verilog学习。
还有啥建议不？谢谢 |
T******T
发帖数: 3066 | 9 www.asic-world.com for tools, simple samples.
Synthesis
【在 O*y 的大作中提到】
: 我下了个Altera 6.5, 看书，( Verilog HDL--Guide to Digital Design & Synthesis
: ), 自己写verilog学习。
: 还有啥建议不？谢谢
|
T******T
发帖数: 3066 | 10 SystemC 俺也用了几年，觉得不错，可惜后来换了几个公司发觉貌似没有很普遍，
cadence也比较在
推广system-verilog.
VERILOG
【在 a*****u 的大作中提到】
: 第一个HDL语言学的是VHDL，做FPGA。后来学ASIC时候才改用的VERILOG。但用VERILOG
: 之后就再没有写过一次VHDL。没可比性，做RTL肯定是VERILOG好使。
: ARCHITECTURE LEVEL的MODELING & SIMULATION，我使着觉得SystemC还是比较方便的。
: 不过其实最好是这些都学一下，至于到底用什么，大多是取决你周围的工作环境。
|
|
|
d******d
发帖数: 2210 | 11 SystemC挺好的，一直在用
不如sv普及感觉是当初没有好好挖掘SC在verification方面的应用
所以大家现在都当SC是high level modeling language
也怪C和M，两家合推SC还不如S一家
【在 T******T 的大作中提到】
: SystemC 俺也用了几年，觉得不错，可惜后来换了几个公司发觉貌似没有很普遍，
: cadence也比较在
: 推广system-verilog.
:
: VERILOG
|
z******a
发帖数: 582 | 12 问问大家，学习写 synthesizable verilog 用哪本书好？
我看到amazon上说“Verilog HDL: a guide to digital design and synthesis”这本
书写synthesis 的太少了，主要集中讲语法。 |
a*****u
发帖数: 157 | 13 什么东西可以综合什么东西不能综合，不用看书，实践决定的。多看综合出来的结果，
比较各种写法之间的差异。
做设计的关键是你对你所设计的东西的掌握，比如计算机体系结构，通信系统结构。关
键并非在几行HDL代码该怎么写上，唯手熟而。 |
I***a
发帖数: 704 | 14 Verilog根本不好用(more error prone, easier to have synthesis issues)，
1. Verilog里wire和reg的定义都是全局的，
VHDL里信号的定义是全局的，变量的定义是局部的。
2. Verilog里Blocking/Non-Blocking赋值对wire和reg混用
VHDL里对变量的赋值相当于verilog里的Blocking赋值，
VHDL里对信号的赋值相当于verilog里的Non-Blocking赋值，
quality.
15-
【在 T******T 的大作中提到】
: private sector : mostly verilog, some system-verilog
: Public sector/defense/academic: mostly VHDL
: Verilog
: pro: Much less verbose, more flexible test benching capability.
: con: Less strict, more error prone, easier to have synthesis issues.
: VHDL
: pro: Very strict, less error prone, less headache due to code quality.
: con: Much more verbose than verilog (personaly experience is about 15-
: 20% more lines of code) when describing the same
: circuitry, less flexible test benching capability.
|
y***f
发帖数: 508 | 15 那是coding style的问题。
第一次听到VHDL比verilog好用的说法。虽然我是先学的VHDL。
【在 I***a 的大作中提到】
: Verilog根本不好用(more error prone, easier to have synthesis issues)，
: 1. Verilog里wire和reg的定义都是全局的，
: VHDL里信号的定义是全局的，变量的定义是局部的。
: 2. Verilog里Blocking/Non-Blocking赋值对wire和reg混用
: VHDL里对变量的赋值相当于verilog里的Blocking赋值，
: VHDL里对信号的赋值相当于verilog里的Non-Blocking赋值，
:
: quality.
: 15-
|
S**********n
发帖数: 250 | 16 I am speaking for Verilog
"Verilog里wire和reg的定义都是全局的"
we are not talking about software programming here.
Both Veilog and VHDL are hardware DESCRIPTION language.
So, the only important thing is that you, as the circuit developer, make
sure your requirement analysis and circuit design are correct, then just
pick any language to DESCRIBE it.
That said, only a very small subset of Verilog is used by an engineer to
DESCRIBE a circuit.
Verilog can be viewed as two parts: synthesizable Verilog and non-
synthesizable Verilog.
The non-xxx Verilog is for simulation only.
The main reason synthesizable Verilog provides many alternative ways of
describing a same logic is that it wants to give verilog users the
opportunity to describe the logic in different levels: behavior-, RTL-,
and gate-level.
You can of course try to apply all the syntax you learned to the
description of any one circuit. But what's the point.
Verilog里Blocking/Non-Blocking赋值对wire和reg混用
Actually, nobody cares about blocking/non-blocking assignment if you
stick to the small subset of the language to DESCRIBE your circuit.
The concepts of "Blocking" and "Non-Blocking" only make sense to the
language developers and compiler developers, or entry level circuit
engineers, who for sure will face this question in interview. Other than
that, you don't have to pay attention to it. Just focus on your circuit
and timing diagram.
【在 I***a 的大作中提到】
: Verilog根本不好用(more error prone, easier to have synthesis issues)，
: 1. Verilog里wire和reg的定义都是全局的，
: VHDL里信号的定义是全局的，变量的定义是局部的。
: 2. Verilog里Blocking/Non-Blocking赋值对wire和reg混用
: VHDL里对变量的赋值相当于verilog里的Blocking赋值，
: VHDL里对信号的赋值相当于verilog里的Non-Blocking赋值，
:
: quality.
: 15-
|
T******T
发帖数: 3066 | 17 Believe me, when you get to large SOC type of applications, you'll
soon get really annoyed at VHDL.
Time is of essence, and any unnecessary verbiage and restriction
is a pain in the butt.
【在 I***a 的大作中提到】
: Verilog根本不好用(more error prone, easier to have synthesis issues)，
: 1. Verilog里wire和reg的定义都是全局的，
: VHDL里信号的定义是全局的，变量的定义是局部的。
: 2. Verilog里Blocking/Non-Blocking赋值对wire和reg混用
: VHDL里对变量的赋值相当于verilog里的Blocking赋值，
: VHDL里对信号的赋值相当于verilog里的Non-Blocking赋值，
:
: quality.
: 15-
|
