t*******c
发帖数: 306 | 1 面试被问到两个synchronizer问题，不是太明白，网上又没找到答案，所以请教一下各位
1. 从一个clock domain 往另一个clock domain传数据， 中间使用了用两个flipflop
连在一起做的synchronizer, 可是实际destination接收到的data可能是错误的，比如
1000 传过去， 实际收到的是1001 , 这个问题怎么解决？
2. 是从快的clock domain 往慢的Clock domain传数据 问题更不容易解决 还是从慢的
Clock domain往快的Clock domain传数据更不容易解决？
(我觉得是从快的clock domain 往慢的Clock domain传数据 问题更不容易解决，因为
用慢的clock来capture source的数据的话，可能会丢掉一些数据，不知道对不对？ )
3.从快的clock domain 往慢的Clock domain传数据 怎么来解决？ | h****p
发帖数: 175 | 2 Dual-FF synchronizer is usually used for single-bit signal, such as enable
or go signal. If you have 1000 (4-bit), you need to use asynchronous FIFO
with address pointers encoded with Gray code. | I***a
发帖数: 704 | 3 1. Dual-FF synchronizer is used for "enable" or "go" signals. These signals
are usually singble-bit and metastability of these signals will not cause
the system to malfunction if they will be sampled more than one time.
e.g. : The start conversion signal for ADC0804 "go", which should be 0,0,1,1
,1,1,1,0,0; but the acutally received is 0,1/0,1,1,1,1,1, 1/0,0; the
indeterminism is caused by metastability but it will not be a problem as
whether to start/end the conversion one cycle faster/slower does not matter.
If you want to synthronize data, Dual-FF synchronizer is not the choice.
2, 3. The most mature method to synthronize data now is use asynchronous
FIFO with address pointers encoded with Gray code. This method is failure-
free and does not have requirements on which clock domain should be faster.
":我觉得是从快的clock domain 往慢的Clock domain传数据 问题更不容易解决，因为
用慢的clock来capture source的数据的话，可能会丢掉一些数据"
You messed with clock speed and data speed. data speed <= clock speed
because for many applications you do not have valid data every clock cycle
such as smithwaterman algorithm. | s**********8
发帖数: 155 | 4 赞，一起学习了~~
signals
cause
0,0,1,1
matter.
failure-
【在 I***a 的大作中提到】
: 1. Dual-FF synchronizer is used for "enable" or "go" signals. These signals
: are usually singble-bit and metastability of these signals will not cause
: the system to malfunction if they will be sampled more than one time.
: e.g. : The start conversion signal for ADC0804 "go", which should be 0,0,1,1
: ,1,1,1,0,0; but the acutally received is 0,1/0,1,1,1,1,1, 1/0,0; the
: indeterminism is caused by metastability but it will not be a problem as
: whether to start/end the conversion one cycle faster/slower does not matter.
: If you want to synthronize data, Dual-FF synchronizer is not the choice.
: 2, 3. The most mature method to synthronize data now is use asynchronous
: FIFO with address pointers encoded with Gray code. This method is failure-
| w*****s
发帖数: 433 | 5 赞！太及时了～
正在头痛有关这个的homework | t*******c
发帖数: 306 | 6 谢谢ICusa，果然用asynchronous FIFO可以解决所有data synchronization的问题，不
过不知道除了用这个之外，还有什么好方法可以解决data synchronization的问题？ | t*******c
发帖数: 306 | 7 And why start/end the conversion one cycle faster/slower does not matter? | T******T
发帖数: 3066 | 8 For relatively static(not cycle active) databus synchronization from
fast - slow clock domain, besides using async FIFO (overkill in this
case), you can also use 1) req/ack mechanism, 2) pulse/toggle
synchronizer
CLK A (fast), CLK B (slow), sync request signal to Shepherd the databus
across the clock domain.
1) update/hold databus, issue req (A) -> Dual FF Sync -> req_sync(B)
then safely latch in the databus from A domain. Ack(B) -> Dual FF Sync
-> ack_sync (A), then clear the request.
2) update/hold databus, issue req_toggle (A) -> Dual FF Sync -> XOR ->
req_pulse (B) then safely latch in the databus from A domain. No need
to sync back to clear the original request. Has limitation of toggle
time spacing. | a********e
发帖数: 381 | 9 1)分析下setup hold time
2）用双口RAM |
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