t*******l
发帖数: 3662 | | r********g
发帖数: 1351 | 2 zero miss rate?
u r kidding. Do not you consider the cold start? | t****t
发帖数: 6806 | 3 given access pattern?
【在 t*******l 的大作中提到】
: open question.
| u****u
发帖数: 229 | 4 sure, as long as you have developed Prescience capability through the use of
Melange.
【在 t*******l 的大作中提到】
: open question.
| t*******l
发帖数: 3662 | 5 considering the program is running for a long time and the miss rate is a
statistics, the initial fetch can be ignored.
【在 r********g 的大作中提到】
: zero miss rate?
: u r kidding. Do not you consider the cold start?
| t*******l
发帖数: 3662 | 6 assuming it is for video processing, so at least there are a lot of spatial
localitis for data cache.
for the instructions, let's also assume we have all the profiling statistics
and tracing capabilities, and we also have the power to change whatever we
want including the hardware, the cache's replacement policy, the OS, and
even the complier or how you code your program...
is it possible to achieve 0 miss rate in cache?
【在 t****t 的大作中提到】
: given access pattern?
| t****t
发帖数: 6806 | 7 i wouldn't say impossible, but surely it depends on your cache size vs data
size. I assume your 0 miss rate means for every data used, it's read from
memory once and only once.
Given an access pattern, you can calculate (or simulate) the minimum cache
size you need. For some deterministic case, you can get 0 miss rate. But
other than that, it really depends.
spatial
statistics
we
【在 t*******l 的大作中提到】
: assuming it is for video processing, so at least there are a lot of spatial
: localitis for data cache.
: for the instructions, let's also assume we have all the profiling statistics
: and tracing capabilities, and we also have the power to change whatever we
: want including the hardware, the cache's replacement policy, the OS, and
: even the complier or how you code your program...
: is it possible to achieve 0 miss rate in cache?
|
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