4 openings for senior ASIC engineer with extensive experience in RTL design
and verification. 40nm experience is a plus.
Please mail CV to: j**[email protected]
Thanks.
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【在 L********r 的大作中提到】 : 4 openings for senior ASIC engineer with extensive experience in RTL design : and verification. 40nm experience is a plus. : Please mail CV to: j**[email protected] : Thanks.
