z*****n
发帖数: 447 | 1 类似CPU，FPGA是否也支持Active, Standby, or Sleep等模式，从而在轻负载的时候节
省能源？ |
d****o
发帖数: 1112 | 2 FPGA本身不支持，不过你可以自己写逻辑支持这些功能啊。
【在 z*****n 的大作中提到】
: 类似CPU，FPGA是否也支持Active, Standby, or Sleep等模式，从而在轻负载的时候节
: 省能源？
|
DK
发帖数: 194 | |
T******T
发帖数: 3066 | 4 FPGA has the capability of gated clock conversion, embedded CPU clock gating
wit WFI mode, dynamic clock mux which could be used to switch to a low
rated clock etc.
You can also implement sleep modes by implementing RTC island(with wakeup
capability), and using locally fanned out soft resets to hold all other
blocks in quiescent state. Pretty much the only thing you can not do is to
run the chip at a reduced voltage, or turn off/on the voltage regulators.
Otherwise, you can always figure out a |
a********e
发帖数: 381 | |
a********e
发帖数: 381 | |
T******T
发帖数: 3066 | 7 Just found this Xilinx whitepaper on FPGA power reduction techniques in
Chinese. Worth a read !
http://china.xilinx.com/china/xcell/xl25/xcell25_456.pdf |
z*****n
发帖数: 447 | 8 Thank you guys!
With your information, I find it seems there are two approaches to reduce
power and control energy for FPGA.
One is gated-clock tech, which should be implemented during VHDL development.
Another is to adjust voltage of pins. I find TI provides a reference design
solution called "buck converter",that can be used to adjust the power of
FPGA. |
d****o
发帖数: 1112 | 9 第二个可能不对。。。FPGA一般要求固定的电压，对于core来说往往还要求+/-3%，降低
电压一般不可行
development.
design
【在 z*****n 的大作中提到】
: Thank you guys!
: With your information, I find it seems there are two approaches to reduce
: power and control energy for FPGA.
: One is gated-clock tech, which should be implemented during VHDL development.
: Another is to adjust voltage of pins. I find TI provides a reference design
: solution called "buck converter",that can be used to adjust the power of
: FPGA.
|
z*****n
发帖数: 447 | 10 从资料看，Actel ProASIC3/E and ProASIC3 nano FPGAs 支持通过改变引脚电压，改
变FPGA工作模式，进入Sleep,Standby,Active模式。
http://www.actel.com/documents/PA3_E_LowPower_HBs.pdf
Xilinx现在还不支持这么做，确实这么做也比较Tricky,不过，TI为Xilinx FPGA提供了
一些功控解决方案，比如加个Buck DC/DC Converter.
http://focus.ti.com/analog/docs/gencontent.tsp?familyId=64&genContentId=1069&DCMP=hpa_pmp_general&HQS=Tools+IL+xilinxfpga |
|
|
T******T
发帖数: 3066 | 11 Yeah, but that's vendor's own hardware low power support and if you count on
that solely for power reduction, then you're gonna be tied with that device
family.
I would prefer to do something more generic, and only in addition use the
device specific methods. That way, if your design was ported to another FPGA
family, you wouldn't have to re-design the whole low power architecture.
【在 z*****n 的大作中提到】
: 从资料看，Actel ProASIC3/E and ProASIC3 nano FPGAs 支持通过改变引脚电压，改
: 变FPGA工作模式，进入Sleep,Standby,Active模式。
: http://www.actel.com/documents/PA3_E_LowPower_HBs.pdf
: Xilinx现在还不支持这么做，确实这么做也比较Tricky,不过，TI为Xilinx FPGA提供了
: 一些功控解决方案，比如加个Buck DC/DC Converter.
: http://focus.ti.com/analog/docs/gencontent.tsp?familyId=64&genContentId=1069&DCMP=hpa_pmp_general&HQS=Tools+IL+xilinxfpga
|
T******T
发帖数: 3066 | 12 Ditto dynamo's comment, you might be able to lower the core voltage and the
I/O bank voltages by a small margin, but the stability and I/O SI might
suffer. Not recommended.
降低
【在 d****o 的大作中提到】
: 第二个可能不对。。。FPGA一般要求固定的电压，对于core来说往往还要求+/-3%，降低
: 电压一般不可行
:
: development.
: design
|
d****o
发帖数: 1112 | 13 If he really want to do low power design, microcontroller is much better
choice.
the
【在 T******T 的大作中提到】
: Ditto dynamo's comment, you might be able to lower the core voltage and the
: I/O bank voltages by a small margin, but the stability and I/O SI might
: suffer. Not recommended.
:
: 降低
|
T******T
发帖数: 3066 | 14 why micro-controller ? I'm assuming besides the low power requirements,
he's got a separate digital design to do which requires a PLD.
better
【在 d****o 的大作中提到】
: If he really want to do low power design, microcontroller is much better
: choice.
:
: the
|
d****o
发帖数: 1112 | 15 microp-controller or processor is far more flexible to deal with low power.
FPGA definitely comsumes more power.
【在 T******T 的大作中提到】
: why micro-controller ? I'm assuming besides the low power requirements,
: he's got a separate digital design to do which requires a PLD.
:
: better
|
T******T
发帖数: 3066 | 16 Well, if he doesn't need complicated custom logic then a generic micro-
processor would do, otherwise, not much choice but to use a PLD.
power.
【在 d****o 的大作中提到】
: microp-controller or processor is far more flexible to deal with low power.
: FPGA definitely comsumes more power.
|
