s*****i
发帖数: 28 | 1 My group has multiple job openings for ASIC Physical Design Engineer (Back-
end) in a processor group in Bay area. If you're interested, please contact
me
through BBS email system first. at least 1 year experience required. No NCG
at this time.
VLSI/Physical Design Engineer
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
RESPONSIBILITIES:
• Ownership of design floor planning, synthesis, DFT, place and
route, clock and power distribution, static timing analysis, signal
integrity analysis, physical verification.
• Contribute to developing physical design methodologies and RTL to
GDS flow automation. | m******e
发帖数: 106 | 2 vulcan?
contact
NCG
【在 s*****i 的大作中提到】
: My group has multiple job openings for ASIC Physical Design Engineer (Back-
: end) in a processor group in Bay area. If you're interested, please contact
: me
: through BBS email system first. at least 1 year experience required. No NCG
: at this time.
: VLSI/Physical Design Engineer
: This position requires an understanding of RTL to GDS flows, CMOS device
: operation and advanced layout rules.
: RESPONSIBILITIES:
: • Ownership of design floor planning, synthesis, DFT, place and
| b*****i
发帖数: 318 | 3 I send a BBS mail to you, please check. thanks |
|
