由买买提看人间百态

boards

本页内容为未名空间相应帖子的节选和存档,一周内的贴子最多显示50字,超过一周显示500字 访问原贴
JobHunting版 - 【工作机会】Staff Engineer – Digital and Mixed-Signal Design- Portland
相关主题
Digital/Mixed Signal Design Engineer 加州job opening - Wireless communication designer (转载)
贴一个非主流的position openingmultiple openings in ASIC design(Santa Clara) (转载)
Open position (转载)[招聘]EE专业多个职位
现在招人很难啊诚心求数字 IC 职位内推 (Verilog / RTL design)
找工作真烦躁这周两个on-site,据说这里求bless很灵的
数字IC工程师的技能树 zzWe are hiring
Job Opening in Broadcom: Principal Logic Design Engineer - SATA Expert招人 - two positions
【工作机会】EDA R&D Engineer in Synopsys Inc.Job opportunity in Bay area
相关话题的讨论汇总
话题: 8226话题: design话题: experience话题: signal话题: strong
进入JobHunting版参与讨论
1 (共1页)
s*******u
发帖数: 692
1
Staff Engineer – Digital and Mixed-Signal Design- in Portland
Experience:
• MSEE or PHD with minimum of 6+ years experience in deep sub-micron
mixed signal design
• High speed digital PMA/PCS design experience including one or more
of the following PHY architecture: Serdes, DDRx, LPDDRx or RF.
• Knowledge & hands-on experience with one or more of the following IO
protocols: PCIe, SATA, USB, SGMII, CEI, FC, Interlaken, XAUI, XPON, DDR3/4,
LPDDR3/4, Intel PIPE 3.0 or above.
• Knowledge and hands-on experience on digital physical media
attachment (DPMA) from architecture definition, RTL coding, logic & mixed
signal verification, IP collateral generation, to post-silicon validation at
both component & system level.
• A track record in delivering high volume commercial products from
architecture definition to post-silicon product qualification, & working
knowledge in industry best practices
• Previous experience in TSMC/UMC’s 40nm process or more advanced
node and Hard
IP’s SoC/system integration & validation flow is a strong plus.
• Past experience in supporting deal acquisition and external customer
engagement is a must.
Skill:
• Strong fundamental in digital, mixed signal and ASIC design &
verification.
• Strong coding skill in Perl, C, Verilog, System Verilog. Past
experience with Python, Verilog-AMS, Verilog-A is a strong plus.
• Experience with tools/flows such as VCS, Design/RTL compiler,
Formality, CDC,
Discovery-AMS, LINT, UVM/OVM/VMM, B-scan, UPF & Scan/BIST , DFT, FPGA flow.
• Past experience with one of more of the following buses: I2C, AMBA
AXI/APB/AHB, PCS, TAP/JTAG, Boundary scan, Memory-mapped-IO,
• Knowledge in digital signal processing, control theory, system
behavior modeling, power management & power-up sequence, clocking and data
pipeline/latency, and IO’s training algorithm is a strong plus
• Knowledge of Physical implementation flows, such as Synthesis, floor
-planning, design constrain, CTS, ICC, design/timing convergence, and
reliability flows.
• Creative design and problem solving ability delivering the highest
level result across power, performance and area
• Strong communication and presentation skills. Ability to work
independently with local and international teams under different time zone
and language background.
• Ability to work across all functional levels. Highly disciplined and
self-motivated. Able to support occasional domestic or international travel
per business requirement.
请站内或者Email [email protected]
1 (共1页)
进入JobHunting版参与讨论
相关主题
internships (summer 2013) & senior engineer opening for Xilinx (bay area, CA)找工作真烦躁
Hiring: Modeling Engineer数字IC工程师的技能树 zz
求IBM内推Job Opening in Broadcom: Principal Logic Design Engineer - SATA Expert
Senior ASIC Design Engineer opening --Santa Clara, CA【工作机会】EDA R&D Engineer in Synopsys Inc.
Digital/Mixed Signal Design Engineer 加州job opening - Wireless communication designer (转载)
贴一个非主流的position openingmultiple openings in ASIC design(Santa Clara) (转载)
Open position (转载)[招聘]EE专业多个职位
现在招人很难啊诚心求数字 IC 职位内推 (Verilog / RTL design)
相关话题的讨论汇总
话题: 8226话题: design话题: experience话题: signal话题: strong