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Highly reputational company with very competitive compensation for all
positions.
Please send in your resume and position/positions you like to apply to my
email address below.
h*******[email protected]
All resumes will be deliver to hiring manager directly. Act fast!
Thanks!
Silicon Engineering Group
Sr. Physical Design Timing Engineer
Timing (STA) Manager
Senior Physical Design Engineer
CAD Manager - Front-End Design and Verification
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Sr. CAD Licensing Engineer
Sr. CAD Engineer – STA
GPU Micro Architect
Design Verification Implementation Engineer
RTL Design Engineer
Analog IP Validation/Characterization Engineer
Senior RF IC Design Engineer
Logic Implementation/ Synthesis Engineer
Design Verification Infrastructure Engineer
Sr. Physical Design Engineer
Formal Verification Engineer
Video Compression Validation Engineer
Validation Engineer-GPU Compiler (Backend)
Silicon Validation ISP Engineer
Silicon Validation Software Engineer (specializing in Graphics)
Silicon Validation: Embedded Kernel Debug Engineer
Silicon Validation-Debug/Triage Engineer
Physical Design – Electrical Methodology
Processor Verification Engineer
Processor Bring Up/Validation Engineer
Processor Random Testing Engineer
CPU Implementation Engineer
Design For Test, Processor Project Owner
CPU Physical Integration Engineer, Processor Project
Library Development Lead
Signoff Methodology Driver
SoC Test Engineer
DRAM Product Engineer
Embedded Software Automation Engineer
Product Engineer
Signal Integrity Engineer
IC Clock Design Engineer
ADC/DAC Analog Designer
High-speed Analog IC Design Engineer
Analog PLL Design Engineer
Analog IP Validation/Characterization Engineer
Analog IP/Silicon Engineer
Performance Analysis Engineer
Silicon Vendor Management Engineer
Senior Product Engineer
VLSI Design Manager
Analog Chip Development Engineer
Unit Level Design Verification Engineer
Logic Design Engineer - Orlando
Logic Design Engineer - San francisco bay area
GPU Micro Architect
Logic Implementation Engineer - Orlando
Logic Implementation Engineer - San francisco bay area
Performance Analysis Engineer - Orlando
Performance Analysis Engineer - San francisco bay area
Top Level Design Verification and Debug Engineer - Austin
Top Level Design Verification and Debug Engineer - Orlando
Top Level Design Verification and Debug Engineer - San francisco bay area
Design Verification Engineer - Austin
Design Verification Engineer - Orlando
Design Verification Engineer - San francisco bay area
Site Manager - Orlando
Site Manager - San francisco bay area
Sr. Physical Design Timing Engineer
Req: 27817123
In this role you will be responsible for all aspects of timing including,
working with designers for timing changes,
helping construct/modify flows, timing analysis and timing closure.
Core Responsibilities:
• Working with design teams to understand and debug constraints,
facilitate logic changes to improve timing
• Working with Physical Design team, highlighting issues and best
practices
• Help create timing ECO’s for project tapeout
• Create/maintain scripts and methodologies for analysis and runs
• Create documentation and help with guidelines/specs
• Deep analysis of timing paths to identify key issues
• Implement timing infrastructure
Qualifications:
The ideal candidate will have 5-10 years of hands on experience in STA.
• Familiar with all aspects of timing of large high-performance SoC
designs in sub-micron technologies
• Needs to be proficient in STA and methodologies for timing closure,
and have a good understanding of noise,
cross-talk, and OCV effects, among others
• Familiar with circuit modeling, including SPICE models and worst-
case corner selection
• Programming with Perl, TCL
• Experience with large design STA and Timing Closure
• Familiarity with ECO techniques and implementation
• Good communicator who can accurately describe issues and follow them
through to completion
Education:
MSEE or equivalent is required.
Timing (STA) Manager
Req: 27816798
In this highly visible role, you will be the manager responsible for timing
signoff of a highly complex SOC utilizing
state of the art process technology.
Core Responsibilities:
• As the manager of the Timing Signoff team, you would be responsible
for:
• Part of a design team that defines the overall clocking architecture
of the SOC.
• Full understanding of the design structures and how to analyze it.
• Owning signoff closure for both timing & SI for the SOC.
• Owning the STA & margining methodology.
• Lead/build/grow a highly talented team of engineers.
• Resource & scheduling planning, and flawless execution to the plan
• Interface with the CAD/technology teams for flow bring up and
validation
Qualifications:
• The ideal candidate will have 10+ years of STA signoff experience,
with recent successful tapeouts in deep submicron
technologies.
• Expert in STA timing & methodologies. Actual recent hands on
experience required.
• Strong knowledge of PD construction & analysis flows and methodology
• Proven ability to manage a STA timing team.
• Proven ability to execute to stringent schedule requirements.
• Strong communication skills.
• Experienced in industry standard tools used and their capabilities &
underlying algorthms.
• Multiple successful chip tapeouts using deep submicron technologies
Education:
MSEE or equivalent is required.
Senior Physical Design Engineer
Req: 27799509
In this role you will be responsible for all aspects of timing including,
working with designers for timing changes,
helping construct/modify flows, timing analysis and timing closure.
Core Responsibilities:
• Working with design teams to understand and debug constraints,
facilitate logic changes to improve timing
• Working with Physical Design team, highlighting issues and best
practices
• Help create timing ECO’s for project tapeout
• Create/maintain scripts and methodologies for analysis and runs
• Create documentation and help with guidelines/specs
• Deep analysis of timing paths to identify key issues
• Implement timing infrastructure
Qualifications:
• The ideal candidate will have 5-10 years of hands on experience in
STA.
• Familiar with all aspects of timing of large high-performance SoC
designs in sub-micron technologies
• Needs to be proficient in STA and methodologies for timing closure,
and have a good understanding of noise,
cross-talk, and OCV effects, among others
• Familiar with circuit modeling, including SPICE models and worst-
case corner selection.
• Programming with Perl, TCL
• Experience with large design STA and Timing Closure
• Familiarity with ECO techniques and implementation
• Good communicator who can accurately describe issues and follow them
through to completion
Education:
MSEE or equivalent is required.
CAD Manager - Front-End Design and Verification
Req: 26034883
As a manager in our CAD Methodology Group, you will be responsible for a
team of CAD engineers that build
front-end design and verification flows. You will use your hands-on skills
to help architect, develop, maintain and
enhance flows for RTL design and verification.
The overall team responsibility includes automation of flows for RTL
regression, Design-For-Test capabilities, formal
verification, synthesis and timing flows. You will manage the deliverables
of the team, maintaining schedules for
delivery and working in a cross-functional environment.
Core Responsibilities:
In this high visible role, you will:
• Have overall responsibilities of managing a solid team that develops
, maintains and enhances flows for all aspects
of front-end design & verification.
• Utilize your hands-on skills to help architect, develop, maintain
and enhance flows for RTL design and verification.
• Coordinate effort of validating flows, enhancing for productivity
and supporting design activities.
• Hire, manage growth, and develop team members, as well as interact
with other design & CAD managers for
collaboration.
Qualifications:
• Typically requires 10+ years of industry experience in chip design
flow development, and at least 5+ years of
management of CAD teams.
• Must have efficient hands-on scripting experience in any of the
following: Perl or TCL or C or Makefile.
• Strong expertse in RTL verification, DFT and/or synthesis flows.
• Requires a deep understanding of the Front-End chip design process
• Various technology node SoC or CPU tapeout experience required.
Education:
MS/BS Degree in technical discipline.
Sr. CAD Engineer - Place & Route / Physical Design Engineer
Req: 26026602
In this highly visible role, you will be enabling a processor design effort
primarily interfacing with the Physical Design
team, with a critical impact on getting functional products to millions of
customers quickly.
Core Responsibilities:
You will utilize your hand-on skills enhancing and supporting the physical
design flow from gate level netlist
through GDS sign-off. Responsibilities will include:
• Developing and integrating new features in the PNR flow.
• Resolving project specific issues within the build and sign-off
flows.
• Releasing flow updates to projects.
• Working with other CAD engineers to coordinate development and
support efforts.
Qualifications:
• Typically requires 10+ years of experience in CAD P&R flows, or
Design P&R
• Expertise in one or more PNR tools.
• Experience closing a physical design - timing, noise, physical
verification, EM/IR/IVD.
• Experience using or supporting sign-off tools for design closure.
• Proficiency with Tcl or Perl scripting languages, Python or C++ is
considered a plus.
• Experience with Makefiles.
Education:
MS/BS Degree in technical discipline.
Sr. CAD Licensing Engineer
Req: 26623621
In this highly visible role you will be the primary coordinator of licenses,
compute resources and disk space across
multiple design sites worldwide.
Core Responsibilities:
In this role, you will:
• Establish standardized license, compute and disk space planning
model for all organizations.
• Work with IT to develop diagnostics/health check dashboards for all
elements of compute infrastructure.
• Manage compute farm queue configurations as they relates to license
usage, priorities, and group allocations/
reservations.
• Drive disk space reclamation and data archiving, consistent with
records retention policies.
• Work with IT organization to standardize computer server
requirements and optimize server configurations.
• Track resource usage against plan.
• Regularly report usage and update requirements with design community
• Manage OS version compatibility across compute farm with respect to
EDA vendors’ roadmaps.
• Manage EDA tool installs and QA against license and OS version
compatibility
• Proactive management and execution of license key downloads,
refreshes, and installs.
Qualifications:
• Fluency in PERL, Linux, SQL, Web-based charting, Excel.
• Experience managing batch queuing systems (LSF, RTDA, Sungrid) for
EDA tool flows.
• IT background - at least an understanding of disk allocation, server
selection and configuration.
• Excellent communication skills to coordinate with design teams and
management.
Education:
MS / BS Degree
Sr. CAD Engineer – STA
Req: 27990640
Location: Austin, TX
In this role you will be responsible for all aspects of timing including,
working with designers for timing changes,
helping construct/modify flows, timing analysis and timing closure.
Core Responsibilities:
• Working with design teams to understand and debug constraints,
facilitate logic changes to improve timing
• Working with Physical Design team, highlighting issues and best
practices
• Help create timing ECO’s for project tapeout
• Create/maintain scripts and methodologies for analysis and runs
• Create documentation and help with guidelines/specs
• Deep analysis of timing paths to identify key issues
• Implement timing infrastructure.
Qualifications:
• The ideal candidate will have 5-10 years of hands on experience in
STA.
• Familiar with all aspects of timing of large high-performance SoC
designs in sub-micron technologies
• Needs to be proficient in STA and methodologies for timing closure,
and have a good understanding of noise,
cross-talk, and OCV effects, among others
• Familiar with circuit modeling, including SPICE models and worst-
case corner selection.
• Programming with Perl, TCL
• Experience with large design STA and Timing Closure
• Familiarity with ECO techniques and implementation
• Good communicator who can accurately describe issues and follow them
through to completion
Education:
MSEE or equivalent required.
Design Verification Engineer
Req: 26044966
Location: Orlando, FL
In this highly visible role, the Functional Verification Engineer will be
responsible for the pre-silicon verification of
embedded graphics cores.
Core Responsibilities:
• Support the design through RTL development and into production
• Develop verification plans, create verification test bench
components, generate tests, run simulations, and debug
design issues
• Create functional coverage points, analyze coverage, and enhance
test environment to target coverage holes
• Provide in-depth knowledge of architecture, implementation,
verification, and debug
• Utilize skills including UNIX and Perl to create efficient,
automated verification flows
• Apply knowledge of hardware description languages (VHDL/Verilog),
hardware verification languages
(SystemVerilog/UVM/OVM), and logic simulators to verify complex designs
Qualifications:
• Verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL;
Specman experience is a plus
• Expertise with various HDL simulators and waveform viewers like
NCSIM, ModelSim, VCS, DVE, Verdi
• Perl, Shell scripting, Makefiles, TCL
• Good knowledge of Computer Architecture, General Purpose
Microprocessor and Memory sub-system microarchitecture
• Experience defining coverage space, writing coverage model,
analyzing results
• Graphics architecture and programming (OpenGL/OpenCL) is a plus
Education:
BSEE/MSEE 3+ years of experience preferred.
GPU Micro Architect
Req: 27985864
Location: Orlando, FL
In this highly visible role, you will be responsible for development of
power efficient, high performance 3D graphics
processors.
Core Responsibilities:
You will be responsible for developing and designing graphics processors.
Responsibilities will include:
• Design and analysis of hardware and software graphics pipelines
• Performance measurement and analysis
• Develop application programming and graphics drivers
Qualifications:
The ideal candidate will possess a Master’s degree and ten plus years of
experience in graphics micro-architecture.
• OpenGL application programming and graphics driver tuning experience
• Expertise in performance measurement and analysis of GPU micro-
architectures and complex 3D scene workloads
• Proficiency with vendor synthesis tools
• Experience designing/analyzing hardware and software graphics
pipelines
• Expertise in floating-point/numerics with regards to graphics image
quality
• Expert in several major sub-units in a high-performance 3D graphics
processor.
• Possesses understanding of processor performance intricacies across
a broad set of workloads.
Education:
MS EE/CE required.
Design Verification Implementation Engineer
Req: 27989694
Location: Austin, TX
In this highly visible role you will be the primary coordinator of licenses,
compute resources and disk space across
multiple design sites worldwide.
Core Responsibilities:
• Verification concepts, strategies, and flows
• Writing, executing, and tracking to test plans
• Simulation-based RTL verification
• Reading and writing Verilog and VHDL
• Writing and maintaining testbenches and BFMs
• Writing checkers
• Generating stimulus
• Implementing and analyzing coverage
• Triaging and debugging fails
• Running and analyzing the results from lint tools
• Gate-level Simulation and debug
• Zero-delay and timing annotated
• Power intent verification
• Verifying arrays
• Simulation approaches
• Functional equivalence between behavioral models and implemented
designs
• Design For Test (DFT) Verification
• General DFT knowledge
• Verification of MBIST and redundancy
• Verification and debug of ATPG
• Property verification tools and flows
• Logical equivalence tools and checking
• Flows and setup
• Debugging using schematics and code analysis
• Integrating hierarchical designs
• Communicating and documenting
• Identifying and resolving verification holes
• Scripting and software engineering
Qualifications:
• 5+ Yrs. of relevant DV experience
• Tools: Spyglass, ESP, Formality, Conformal, Jasper, VCS/IES
• Languages: Verilog, VHDL, System Verilog or C++
• Scripting: perl, TCL, make
• Configuration management tools: Perforce
Education:
§ BSEE/MSEE
RTL Design Engineer
Req: 27987953
Location: Austin, TX
In this role, the RTL Design Engineer will be responsible for delivering
quality IP in order to meet project functional,
timing, area, and power goals.
Core Responsibilities:
The responsibilities encompass all phases of design including:
• micro-architecture definition
• specification
• implementation
• simulation
• synthesis
This individual will collaborate with the architecture team, functional
verification team, and physical design team.
Qualifications:
• Knowledgeable in modern design techniques and energy-efficient/low-
power logic design
• Strong background in computer architecture including one or more of:
• high-speed CMOS processor and controller blocks like cache
controllers, bus-interface- subsystems,
• integer and floating point numeric units, digital filters, graphics
processors, crossbar fabrics and other highspeed
data-path and control units.
• Expertise in logic optimization, synthesis, timing analysis, floor-
planning.
• Fluent with RTL Verilog/VHDL syntax and hardware modeling issues
• Familiarity with logic simulation and debug environments as well as
formal verification.
• Ability to work well in a team and be productive under aggressive
schedules.
• Should exhibit excellent communications skills, and be self-
motivated and well organized.
Education:
PHD/MSEE preferred, plus 5+ years of industry experience; or BSEE plus
equivalent level of experience.
Top Level Design Verification and Debug Engineer
Req: 27989184
Location: Austin, TX
In this highly visible role, the Top Level Design Verification and Debug
Engineer will be responsible for the presilicon
verification of embedded graphics cores.
Core Responsibilities:
• Support the design through RTL development and into production
• Develop verification plans, create verification test bench
components, generate tests, run simulations, and debug
design issues
• Create functional coverage points, analyze coverage, and enhance
test environment to target coverage holes
• Provide in-depth knowledge of architecture, implementation,
verification, and debug
• Utilize skills including UNIX and Perl to create efficient,
automated verification flows
• Apply knowledge of hardware description languages (VHDL/Verilog),
hardware verification languages (Specman/
System Verilog), and logic simulators to verify complex designs
Qualifications:
• Verification language such as Specman, SystemVerilog, Verilog/VHDL
• Expertise with various HDL simulators and waveform viewers like
NCSIM, ModelSim, VCS, DVE, Verdi
• Perl, Shell scripting, Makefiles, TCL
• Good knowledge of Computer Architecture, General Purpose
Microprocessor and Memory sub-system microarchitecture
• Experience defining coverage space, writing coverage model,
analyzing results
Education:
BSEE/MSEE 3+ years of experience preferred.
Analog IP Validation/Characterization Engineer
Req: 12902654
In this highly visible role, you will perform lab characterization and
validation of embedded circuits; interfacing
with many disciplines to launch the world’s premiere mobile computing chips.
Core Responsibilities:
You will be part of a small team responsible for:
• Bench test, debug, and characterization of embedded on-chip circuits
(PLLs, DLLs, clocks, memory interfaces, and
I/Os).
• In-system PI/SI measurements for correlating with simulation models.
• Debug compliance test failures of standard interfaces (USB, MIPI,
DisplayPort).
• Setup, debug, and maintain lab system test environment.
• Development of bench top characterization tests exercising on-chip
circuits through a combination of FPGA,
JTAG, and analog interfaces
• Development and execution of scripts to automate tests, extract and
store results, and generate reports using
database and analysis tools.
• Preparation of reports related to characterization and debug
• Interface with chip design teams, system HW and SW design teams, ATE
PE
Qualifications:
The ideal candidate will have the following qualifications:
• Min 5 years experience in test development, debug, and reporting
• Expertise in test and script development, PERL / TCL preferred
• Expertise in using electronic measurement equipment
• Expertise with test data analysis platforms and databases
• Expertise in testing/characterizing PLLs, DLLs, SERDES, and memory
interfaces
• Expertise in testing/characterizing control loops for various
voltage regulator topologies (LDOs, bucks, multiphase
bucks).
• Lab skills for soldering/instrumenting systems for test or debug.
• Strong initiative and ownership of responsibilities, productive,
able to meet aggressive deadlines
• Good written and verbal communication skills
• Emphasis on quality and self-checking of scripts, test patterns, and
reports
• Matlab/DSP experience is a plus
Education:
BSEE / MSEE is required.
Senior RF IC Design Engineer
Req: 27777051
In this highly visible role, you will be at the center of a silicon design
group with a critical impact on getting functional
products to hundreds of millions of customers quickly.
Core Responsibilities:
As an RF IC design engineer, you will responsible for providing RF solutions
for wireless chips. Responsibilities include:
• Work with platform architects, system groups and digital design
group to define the requirements for RF and
baseband blocks based on the system requirement.
• Work with technology team on process selection for the target device.
• Work with the front end design and chip integration group to
integrate the analog and mix-signal IPs into the
chips
• Design various component blocks of Tx and Rx signal path
• Consult on RF analog issues across Apple
Qualifications:
The ideal candidate will have 5+ years of analog and mix signal design
experience, with 3 years in leading RF
CMOS design.
• Direct experience designing and bringing into high volume production
, ZIF RF transceivers in deep sub-micron
RFCMOS technology, specifically for WLAN & BT applications including dual-
band and MIMO WLAN applications.
This includes design of on-chip LNAs and PAs as well as calibration methods
associated with such high performance
wireless systems and ZIF designs. Experience should also include
understanding of DFT and DFM techniques
for high volume production environment.
• Extensive knowledge of all or many of the following fields:
• Deep understanding in system specification and able to work with
system architects to translate system
requirement into circuit requirement at IC level; Requires strong
understanding of impact of modulation
type to radio architecture and requirements.
• Familiar with various RF transceiver architectures and their trade-
offs; Demonstrate the capability to work
with digital design group for an optimum partition between digital and
analog domain;
• Deep understanding of fundamentals of RF CMOS implementation, and
basic building blocks, including
LNAs, mixers, VCOs and DCOs, LO and PAs;
• Deep understanding of RF device modeling, including but not limited
to device noise parameters, inductor
modeling. Insights into packaging effects, supply isolations, high frequency
ESD structures, and circuit layout
for optimum RF performance;
• Requires strong knowledge of desense and able to work closely with
board RF/HW/Antenna teams to optimize
board layouts for desense mitigation. Also, has experience with desense
mitigation with integrated
PMUs/DSPs (i.e. substrate isolation, return loops, package isolation,
frequency planning, etc).
• Familiar with mix signal mode verification methodology
• Extensive experience in Si characterization and debug
• Ability to drive strong production test/QA methodologies.
• Extensive experience in IP sourcing and management
Education: BSEE is required. MSEE/Ph. D is preferred.
Logic Implementation/ Synthesis Engineer
Req: 27987735
Location: Austin, TX
This position will be responsible for all phases of front-end logic design,
with the primary focus on RTL to gatelevel
netlist creation.
Core Responsibilities:
• Optimize designs to achieve power, area, timing goals
• Simulation/Debug of large complex designs
• Collaborate effectively with different functional teams
Qualifications:
• The ideal candidate will have 5-10 years of hands on experience in
front-end design synthesis and large chip
integration.
• Proven expertise in advanced synthesis techniques to achieve
aggressive low power, area, and timing goals.
• Ability to optimize designs for best in class in low power and high
performance with logically equivalent RTL
transforms.
• Proficiency in: static timing analysis, Verilog/VHDL, formal
verification, lint checks, multi-clock and power domain
designs.
• Familiarity with simulation, coverages, debugging tools, and working
closely with DV team.
• Insight into physical design implications: floor-planning, placement
, congestion, clock trees and setup/hold timing
closure.
• Experience with DFT insertion, multi-mode timing constraints, and
ECO implementation.
• Ability to collaborate effectively with different functional teams
and strong written/verbal communication skills.
• Knowledge of architecture and micro-architecture of CPUs, GPUs or
DSPs desirable.
Education:
PHD/MSEE, or BSEE with relevant industry experience.
Design Verification Infrastructure Engineer
Req: 27990604
Location: Austin, TX
In this highly visible engineering role, you will be responsible for
creating and maintaining a complex design verification
automation infrastructure and flow across all verification domains for
multiple projects. Design verification
today is dealing with ever-increasing design challenges that require a
scalable infrastructure and more focused
support. It is especially challenging to manage and interpret large volumes
of verification metrics to increase visibility
and quality of verification process.
Core Responsibilities:
As a design verification infrastructure engineer, you will have
responsibilities spanning all aspects of design verification:
• Working with design verification engineers across multiple design
sites to understand requirements and deliver
consistent and uniform solutions throughout the organization
• Defining verification build and run flow for various hierarchies of
the design and test benches
• Working with internal centralized CAD organizations to unify flows
throughout Apple and also drive new requirements
in order to unify flows per organization needs.
• Defining data management infrastructure for verification result
management
• Working with DV leads and engineers to support projects from start
to finish
• Defining and implementing improvements to the infrastructure to stay
ahead of project needs
• Interface with EDA vendors to ensure the tools are properly
integrated to the flow
• Evaluate new verification tools and assess their integration to the
flow
Qualifications:
The ideal candidate will have 5+ years of working/using Digital Design Front
End tools and flows with specific focus
on scripts and automation.
• Knowledge of Design Verification Tools (Simulators, Formal
Verification Tools) on how they work, what data they
produce
• Solid knowledge and hands-on experience on scripting using Perl,
Python, Makefile
• Knowledge about SQL style databases and query language is a plus
• Knowledge of Design Verification Methodology is a plus
• Working knowledge of Verilog and/or VHDL
• Ability to conduct experiments during silicon debug, gathering and
analyzing data; and utilize scripting to support
efficient handling of ATE data
Education:
BSEE / MSEE is required.
Sr. Physical Design Engineer
Req: 27990008
Location: Austin, TX
In this highly visible role, you will be responsible for implementing
complete chip design from netlist to tapeout.
Core Responsibilities:
• Work with FE team to understand chip architecture and drive physical
aspects early in design cycle.
• Work with physical design team, drive methodologies and “best known
methods” to streamline physical design
work, come up with guidelines and checklists, drive execution, and track
progress.
• Be focal point for place and route drive the work among place and
route engineers, set goals and milestones,
plan short and long-term work, understand dependencies between different
domains like top, STA, block place
and route.
• Resolve design and flow issues related to physical design, identify
potential solutions and drive execution.
Qualifications:
The ideal candidate will have 5-10 years of hands on experience in physical
design and large chip integration.
• Needs to be familiar with all aspects of ASIC integration including
Floorplanning, Clock and Power distribution,
global signal planning, I/O planning and hard IP integration.
• Familiar with typical SoC issues such as multiple voltage and clock
domains, ESD strategies, mixed signal block
integration, and package interactions.
• Familiar with hierarchical design approach, top-down design,
budgeting, timing and physical convergence.
• Must have experience on integrating IP from both internal and
external vendors and be able to specify and drive
IP requirements in the physical domain
• Experience with large SoC designs (>20M gates) with frequencies in
excess of 1GHz utilizing state of the art sub
45nm technologies.
• A detailed understanding of database management issues will be
required
• From a CAD tool perspective, experience with Floorplanning tools, P&
R flows, global timing verification and
Physical Design Verification Flows is required.
• Familiar with various process related design issues including Design
for Yield and Manufacturability, multi Vt
strategies and thermal Mgt.
Education:
MSEE or equivalent is required.
Formal Verification Engineer
Req: 26138794
In this highly visible role, you will be at the center of a System-on-a-chip
(SoC) design verification effort interfacing
with design, with a critical impact on getting high quality and bug-free
functional products to millions of customers
quickly.
Core Responsibilities:
As a formal verification engineer owning the complete formal verification
for single or multiple design blocks and
IP’s, you will be responsible for
• Working with SOC and IP design teams to develop a formal micro-
architecture specification
• Developing a comprehensive formal verification test plan
• Proving properties of the design, finding design bugs, and working
closely with design teams to help improve
the micro-architecture
• Architecting novel and innovative solutions for verifying complex
design micro-architectures
• Developing and implementing re-usable and optimized formal models
and verification code base
Qualifications:
The ideal candidate will have the following experience
• Advanced knowledge of SoC and CPU designs, VLSI, and digital logic
design
• Developed formal property proofs on any RISC/CISC architectures
• Deep understanding of pipeline architectures, memory/DMA controllers
, out-of-order and speculative instruction
execution hardware, bus interconnects, and cache coherence mechanisms
• Solid understanding of formal verification technologies and
abstraction techniques
• Knowledge and experience in interpreting hardware specifications and
using temporal logic assertion-based
languages such as SVA or PSL
• Experience in using EDA formal tools and experience in CAD tool
development is a plus
• Proficiency in any scripting language such as TCL/Perl/etc… with
excellent debugging skills
• Strong team player with excellent communication skills
• Passionate! about developing world-class formal verification
solutions
Education:
BS / MS / Ph.D in EE or CS is required.
Video Compression Validation Engineer
Req: 16786634
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish. In this highly visible role, as part of a highly talented team
you will be at the heart of the chip design
effort interfacing with all disciplines (vertical product model) with
critical impact in getting functional products to
millions of customers quickly.
Core Responsibilities:
You will be responsible for system level validation of image signal
processing sub-system in silicon:
• Work closely with the team, review specifications, develop
verification plans.
• Work closely with design & micro-architecture teams to understand
the functional & performance goals of the
design.
• Develop low-level software to validate functionality, conformance &
performance of image signal processing
subsystem.
• Bring-up and debug devices on new hardware platforms.
• Work with cross-functional teams to support product requirements.
Qualifications:
The ideal candidate will have the following experience:
• Develop low-level software to validate functionality, conformance,
and performance of video compression
blocks.
• Bring-up and debug devices on new hardware platforms.
• Work with cross functional teams to support product requirements.
Education:
BSEE or BSCS / MSEE or MSCS with industry experience over 5 years.
Validation Engineer-GPU Compiler (Backend)
Req: 27807175
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish. In this highly visible role, as part of a highly talented team
you will be at the heart of the chip design
effort interfacing with all disciplines (vertical product model) with
critical impact in getting functional products to
millions of customers quickly.
Core Responsibilities:
• Port and implement back end code generation for new ISA
• Develop and maintain constraint based code generator for random
testing
Qualifications:
The ideal candidate will have the following experience:
• 5+ years in compiler backends
• Solid knowledge in computer/system/soc architecture, pipelining, bus
architectures and protocols
• Expert C programmer
• Skilled scripter
• Strong math skills
• Objective C and iOS frameworks knowledge a plus
• OpenGL/OpenCL/CUDA/DirectX API knowledge a plus
• Understanding of the 3D rendering pipeline a plus
Desired Background:
• Experience in LLVM or GCC
• Knowledge of compiler architecture & code generation
• Experience in building tools chains for high performance
architectures
• Experience in building tool chains for embedded platforms
Keywords:
• Codegen, LLVM, GCC, Shader Compiler, OpenGL, OpenCL, CUDA, DirectX,
high performance, tool chain development,
code generator, random testing, instruction sets, graphics
Education:
BS / MS in EE or CS is required.
Silicon Validation ISP Engineer
Req: 7192173
Block and system-level validation of image sensor data (camera) processing
subsystems in silicon.
Core Responsibilities:
You will be responsible for system level validation of image signal
processing sub-system in silicon:
• Work with logic designers to understand the operation of image
processing pipelines at the block and system
levels.
• Investigate the use cases, system-level operation, performance
requirements
• Develop low-level software to validate functionality, conformance,
and performance of image sensor processing
subsystems.
• Work with other members of the validation team to incorporate your
tests into system-level tests.
• Bring-up and debug devices on new hardware platforms.
Qualifications:
The ideal candidate will have the following experience:
• Strong software skills in C/C++
• Experience with image sensor processing hardware pipelines (e.g. raw
image processing, cameras, MIPI).
• Experience with hardware/software interaction.
• Knowledge of image formats and color spaces.
• Embedded software experience is a must. Device driver experience a
plus.
• Interest in writing software to validate the correct operation of
hardware.
Education:
BSEE or BSCS / MSEE or MSCS with industry experience over 5 years.
Silicon Validation Software Engineer (specializing in Graphics)
Req: 7192021
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish.
Core Responsibilities:
The ideal candidate would would be able to lead the development of low level
code to push CPU data motion
through caches, memory controllers, and various coherent and/or non-coherent
agents. A deep understanding of
CPU architecture as well as cache hierarchy is a must.
Qualifications:
The ideal candidate will have the following experience:
• Development and testing experience
• Solid knowledge of OpenGL, display interfaces in Linux.
• Familiar with Linux driver architecture
• Experience with exercising/validation of system from user space,
knowledge of user space API
• Skilled C programmer
• Familiarity with ARM architecture a plus
Education:
Bachelor's or Master's degree in EE or CS with 5+ years of graphics.
Silicon Validation: Embedded Kernel Debug Engineer
Req: 27880992
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish.
Do you thrive at the interface of hardware and software and love analyzing
problems and root-causing complex
bugs that result from their interactions? A sort of jack-of-all-trades, are
you part kernel or embedded firmware
hacker, part lab junkie, and have people skills to boot? Come talk to us.
We are looking for superstars in the growing Silicon Validation Debug and
Regressions (SiVal D&R) team. SiVal D&R
performs SoC bug triage, silicon characterization, and maintains test racks.
As a Silicon Validation iOS Debug Engineer, you will lead debug and triage
of SoC bugs in Silicon, FPGA and Emulation
environments with focus on issues first reported in the iOS kernel and
bootloader environments.
Core Responsibilities:
In your job as debug and triage lead, your goal is to quickly and
effectively root-cause issues believed to be SoC
issues. To this end, you will harness and modify production and test
software from other teams.
• You will work with experts from many teams to understand SoC and
system behavior: iOS kernel/driver, Silicon
Validation IP test SW, Factory diagnostics, SoC architecture, SoC IP design
and verification, FPGA Prototyping,
Systems Integration, board designers, etc.
• To process failed units from factory burn-in tests, you will enhance
our automated triage process.
• Your success will be defined by the time to closure of SoC bugs (
wherever the root cause may lie), the
throughput of bugs closed, the relationships you build, and the improvements
you bring about to our test
rack and automated triaging methodologies.
Qualifications:
The ideal candidate will have the following experience:
• C, assembly, system programming, scripting
• UNIX kernel and device driver programming
• Uniprocessor, multiprocessor and computer system architecture
• Lab measurement equipment (oscilloscope, logic analyzer, bus
analyzer)
• Methodical and creative analysis skills
• Enjoy debugging
• People and communication skills
Education:
BS / MS in EE or CS is required.
Silicon Validation-Debug/Triage Engineer
Req: 25590448
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish.
Do you thrive at the interface of hardware and software and love analyzing
problems and root-causing complex
bugs that result from their interactions? A sort of jack-of-all-trades, are
you part kernel hacker, part logic designer,
part lab junkie, and have people skills to boot? Come talk to us.
We are looking for superstars in the growing Silicon Validation Debug and
Regressions (SiVal D&R) team. SiVal D&R
performs SoC bug triage, silicon characterization, and maintains test racks.
As a Silicon Validation Debug and Triage Engineer, you will lead debug and
triage of SoC bugs in Silicon, FPGA and
Emulation environments.
Core Responsibilities:
In your job as debug and triage lead, your goal is to quickly and
effectively root-cause issues believed to be SoC
issues. To this end, you will harness and modify production and test
software from other teams.
You will work with experts from many teams to understand SoC and system
behavior: iOS kernel/driver, Silicon
Validation IP test SW, Factory diagnostics, SoC architecture, SoC IP design
and verification, FPGA Prototyping, Systems
Integration, board designers, etc.
To process failed units from factory burn-in tests, you will enhance our
automated triage process.
Your success will be defined by the time to closure of SoC bugs (wherever
the root cause may lie), the throughput
of bugs closed, the relationships you build, and the improvements you bring
about to our test rack and automated
triaging methodologies.
Qualifications:
The ideal candidate will have the following experience:
• C, assembly, system programming, scripting
• UNIX kernel and device driver programming
• Uniprocessor and multiprocessor computer architecture
• SoC architecture, some IP block knowledge
• SoC design cycle
• Lab measurement equipment (oscilloscope, logic analyzer, bus
analyzer)
• Methodical and creative analysis skills
• Enjoy debugging
• People and communication skills
Education:
BS / MS in EE or CS is required.
Physical Design – Electrical Methodology
Req: 27681366
Core Responsibilities:
• Clock definition & signoff:
• Define clock signoff specification that balances power,
performance, and area requirements.
• Execute simulations chip and partitions level to ensure the clock
spec is implemented correctly.
• Owns clock signoff & waiver process
• Design target:
• Simulate design critical paths with early spice models to determine
critical path scalability.
• Participate in working group discussions for process, voltage,
derates, transistor mix. Using actual design
data to guide the design target selection.
• Routing template:
• Defines electrically the right routing templates.
• Examples include ps/mm for different buffer/inverter combinations.
• Power Grid:
• Define power grid specification that balance IVD and power EM
requirements, schedule, routability, and
CAD complexity
• Simulate power switch leakage, IR, and on/off time to determine
optimal switch size/placement.
• Power Planning:
• Interfaces with power team to understand power requirements of
future projects
• Create design specific leakage and dynamic power targets for each
specific partitions.
• Standard cell requirements:
• Evaluate the project requirements to determine the types of standard
cells that PD team will need: channel
length, VT, low power, high performance.
• Interface with technology team and other design teams determine the
correct set of PVT corners, extraction
corners, timing corners that will be needed for projects
Qualifications:
• Technical leadership in the field. Company wide recognition.
Industry wide recognition a plus.
• Demonstrated experience in various areas of custom design: clock,
power grid, low power design, standard cell
design
• Team player with excellent spoken and written communication skill
• Well rounded design experience in P&R, floorplanning, clock tree
creation, STA, power gating, optimization, formal
verification, EM/IR
• Good understanding of other parts of the design methodology:
synthesis, DFT, DV
• 15 years of hands on experience on custom design of high performance
chips; with multiple, successful chip tape
outs in leading edge technology.
Education:
MSEE required.
Processor Verification Engineer
Req: 27996765
Location: Austin, TX
In this highly visible role, you will be at the center of a chip design
effort interfacing with all disciplines, with a critical
impact on getting functional products to millions of customers quickly.
Core Responsibilities:
As a chip verification engineer owning the verification of a certain area of
functionality in a chip design, you will
have the responsibilities as follows:
• Work closely with architecture and RTL designers on verifying the
functionality correctness of the design
• Develop test plans and test environments
• Develop tests in assembly, C, or vectors according to test plans
• Develop coverage monitors and analyze coverage to ensure all the
test cases in the plans are covered
• Develop checkers or C-base transactor to verify the design
• Write assertions and apply formal verification to the design
Qualifications:
The ideal candidate should have 5+ years of processor verification
experience.
• In-depth knowledge of digital logic design, chip architecture and
microarchitecture.
• Experience with expertise in developing testplans/testbenches, C-
based transactors, and writing/debugging
assembly based tests.
• Experience with advanced verification techniques such as formal and
assertions a plus.
• Experience in silicon bringup a plus.
• Should be a team player with excellent communication skills, be able
to work independently on the verification
efforts for a block/area of the design.
• Some travel may be required
Education:
BS, MS, or Ph.D. in Electrical Engineering, Computer Science, or Computer
Engineering is required.
Processor Bring Up/Validation Engineer
Req: 27996722
In this highly visible role, you will be at the center of a chip design
effort interfacing with many disciplines, with a
critical impact on getting functional products to millions of customers
quickly. You’ll be responsible for silicon
verification/bring up tasks for a CPU. The role includes bring up diag
generation, preparation, lab testing, functional
and physical failure analysis and debugging. You will work on CPU test chips
and the CPU in SOC chips.
Core Responsibilities:
• Prepare diags to run on silicon. The diags span from simple diags
that fit in the L2 cache, to OSes and applications
that run from DRAM. They will target functionality, power, performance, and
physical design characterization
for timing and reliability.
• Test generator for processor verification in a system. The test
generator should mimic real applications and OS
code sequences.
• Deliver silicon bring up test plans
• Work with performance modeling engineers to prepare performance
tests, characterize silicon performance and
debug performance issues on silicon.
• Work with implementation engineers to prepare tests for
characterizing power, timing, and reliability on silicon
and debug any of the physical issues on silicon.
• Work with verification engineers to prepare functionality tests and
debug the functionality issues on silicon.
Qualifications:
The ideal candidate should have 5+ years of processor pre- and post-silicon
verification experience.
• Strong understanding of processor architecture and micro-
architecture.
• Experience designing tests to target specific portions of processor
functionality.
• Excellent skills in root-causing silicon failures.
• Ability to use simulation and emulation to create tests and target
functionality
• Excellent teamwork and communication. Ability to work across teams
to drive a solution.
• Strong programming skills.
Education:
BS, MS, or Ph.D. in Electrical Engineering, Computer Science, or Computer
Engineering is required.
Processor Random Testing Engineer
Req: 27996765
In this highly visible role, you will be at the center of a chip design
effort interfacing with all disciplines, with a critical
impact on getting functional products to millions of customers quickly.
Core Responsibilities:
As a random testing engineer for the processor, you will have the following
responsibilities:
• Work closely with verification team in creating random test
templates and providing random tests in assembly
• Improve existing random test generators or write new test generator
to improve test coverage for various architecture
corner cases in debug features, exceptions, error handling, multiprocessor,
and memory management.
• Develop architecture coverage to direct the test generation.
• Verify some components in a processor design.
Qualifications:
The ideal candidate should have 3+ years of processor verification
experience with the following strengths and
experience:
• In-depth knowledge of processor instruction set architecture and
microarchitecture.
• Strong in C/C++ and PERL programming. Experience is using debuggers.
• Experience with expertise in writing/debugging assembly based tests,
and creating random test generators/
templates.
• Experience in writing instruction set simulator a plus.
• Should be a team player with excellent communication skills, be able
to work independently on creating the test
generator.
Education:
BS, MS, or Ph.D. in Electrical Engineering, Computer Science, or Computer
Engineering is required.
CPU Implementation Engineer
Req: 27997028
Apple’s Silicon Engineering Group (SEG) is hiring talented engineers for
CPU block-level implementation.
Core Responsibilities:
As an implementation engineer you will own or participate in the following:
• Will work extensively with Micro-architects to define memory
subsystem, perform feasibility, make area/
frequency/performance/power tradeoffs and design & balance the pipeline
stages.
• Drive RTL-to-GDS flow through synthesis and place-and-route
targeting aggressive targets for power, performance,
and area.
• Design delivery. Work with cross-functional engineering team to
implement and validate physical design on the
aspects of timing, area, reliability, testability and power.
Qualifications:
The ideal candidate should possess an MS or PhD in Electrical Engineering
with 5+ years of CPU Implementation
experience.
• Familiarity with high performance microprocessor architecture
• Knowledge of logic design principles along with timing and power
implications
• Understanding of low power microarchitecture and implementation
techniques
• Design experience in deep submicron technologies and basic device
physics
• Experience using synthesis & place-route tools
• Experience with scripting in Perl and/or TCL
Education:
BSEE/MSEE is required.
Design For Test, Processor Project Owner
Req: 27997070
In this highly visible role, you will be at the center of a processor design
effort interfacing with all disciplines, with a
critical impact on getting functional products to millions of customers
quickly.
Core Responsibilities:
As a DFT engineer owning the complete DFT solutions for a processor project,
you will have responsibilities spanning
all aspects of processor design:
• Working with SOC DFT team to document processor DFT specifications
and define the SOC-processor test interface
• Developing and implementing DFT architecture
• Implementing DFT infrastructure
• Working with the DV team to verify DFT implementations and implement
ECOs
• Generating structural test vectors and analyzing and improving
coverage
• Working with designers on STA, physical, power and logical issues
• Working with test engineers to bring up test vectors on silicon
• Managing schedules and supporting cross-functional engineering
effort
Qualifications:
The ideal candidate will have 5+ years of DFT experience, leading DFT
efforts for large processor and/or SOC designs.
• Knowledge about industrial standards and practices in DFT, including
ATPG, JTAG, MBIST and trade-offs between
test quality and test time
• Experience developing DFT specifications and driving DFT
architecture and methods for designs
• Knowledge of Verilog and/or VHDL, and experience with simulators and
waveform debugging tools
• Knowledge of industry standards DFT and design tools
• Solid Understanding of design verification (DV) methodologies for
validating DFT implementation in simulation
pre-silicon
• Experience in debugging ATPG patterns, Compressed ATPG patterns,
MBIST, and JTAG/1500 related issues
• Experience with STA constraints development and analysis for DFT
modes and SDF simulations
• Ability to conduct experiments during silicon debug, gathering and
analyzing data; and utilize scripting to
support efficient handling of ATE data
Education:
BSEE / MSEE is required.
CPU Physical Integration Engineer, Processor Project
Req: 27997096
In this highly visible role, you will be at the center of a processor design
effort interfacing with all disciplines, with a
critical impact on getting functional products to millions of customers
quickly.
Core Responsibilities:
As a Full Chip Integration Engineer, you will be participating in the
physical design, integration and verification of
high performance processor project.
Your responsibilities include:
• Full chip floorplan, area optimizations, block partitioning and pin
placements.
• Own chip level place and route database and verification.
• Develop and validate power grid.
• Drive Formal verification, block and full-chip level EM/IR,
electrical verification, and custom layout integration.
• Working with the implementation/CAD team during the entire chip
design cycle to drive signoff closure for
tapeout.
• Work with SOC team to meet IP technical and delivery requirements.
• Participate in establishing CAD and physical design methodologies.
• Participate in flow development for chip integration and analysis.
• Scripting to automate tasks and improve debug efficiency.
Qualifications:
The ideal candidate will have 5+ years of Physical Design, Integration and
verification experience on large processor
and/or SOC designs.
• Knowledge of industrial standards and practices in Physical Design,
including Floorplanning, Partitioning,
Budgeting, Place and Route and Physical verification.
• Experience in developing and implementing Powergrid and Clock
specifications
• Solid knowledge of Low Power Design, Physical construction,
Integration, EM/IR-Drop/Noise, SIGEM analysis,
Formal verification, Physical DRC/LVS verification, and DFM.
• Solid understanding of verification tools such as Conformal LP, LEC,
RedHawk, Calibre.
• Solid understanding of CMOS circuit design. Layout design background
is a plus.
• Working knowledge of Extraction and STA methodology and tools.
• Working knowledge of Computer Architecture.
• Solid understanding of scripting languages such as Perl/Tcl.
• Ability to work well in a team, problem solver and self motivated.
Education:
BSEE / MSEE is required.
Library Development Lead
Req: 27996843
In this role, you will be working on custom digital circuits and library
development. You will work with the team to
implement advanced circuit techniques to improve circuit performance and
optimize dynamic/static power. You
will be driving development of standard cells, custom cells including adder,
multiplier and low power flops. It requires
you to understand the complete library design flow, P&R/timing integration
requirements of library, DFT/
testing aspect of the design. In addition, you will be driving methodology
and CAD flow enhancement for the semi
custom design flow.
In this highly visible role, you will be at the center of a processor design
effort interfacing with all disciplines, with a
critical impact on getting functional products to market quickly.
Qualifications:
The ideal candidate will have 5+ years of circuit design experience in the
CPU environment.
• Knowledge of high performance low power circuit design
• Experience developing standard cells and complex cells including
large adders, multipliers, shifters and ALU
units.
• Responsible for Working with logic/architecture team to gather
specifications and requirements of library
cells
• Knowledge of industry standard library development and design tools
• Solid Understanding of device physics and process
• Good understanding of computer architecture
• Knowledge of STA and P&R tools is a big plus
Education:
BSEE / MSEE is required.
Signoff Methodology Driver
Req: 27996874
Responsible for definition and development of signoff methodology for high-
volume state-of-the-art SOCs and
digital/analog chips. This includes signoff for static timing analysis, IR,
IVD (Instant Voltage Drop), Electro-migration,
Power analysis (dynamic and static), clocking, Analog, physical design
verification, ESD, DFT, fuses, CAD tools, etc.
The job includes definition of the signoff methodology, driving EDA vendors
wherever external tools are used, defining
methodologies based on vendor solution or developing internal value-add
solution in addition to vendor
tools. This involves working directly with designers, technical leads, CAD
engineers, and technologists, to understand
& develop the right solution for the product.
Core Responsibilities:
• Should have strong technical background involving all aspects of
chip design.
• Should be excellent in planning and tracking of own deliverables.
• Should be able to seed new ideas in current assignment and
continuously think beyond current assignment on
look ahead solutions.
• Must be highly focused and remain committed towards achieving
project goals.
• Good communication and presentation skills and team work.
• Strong in design flow development and CAD tools.
• Should have good interpersonal skills to be able to interact
efficiently with the immediate team members.
• Should be willing to seek alignment in situations of conflict of
opinions with cross-functional teams.
Qualifications:
• Demonstrated leadership and proven track record delivering full chip
from specifications to bring up and testing.
• Must have lead multiple tape outs.
• Hands-on experience in all phases of chip development, including
definition, micro-architecture, design, verification,
DFT, implementation, and backend analysis.
• Experience with digital and analog design is a strong plus.
• Must have experience with CAD tools and design flows.
• Must have strong written and oral communication skills, leadership
qualities, project management, and team
participation skills.
Education:
BS/MS EE or equivalent with 15+ years of experience.
SoC Test Engineer
Req: 27996921
Design and debug of ATE programs and hardware for debug, characterization,
qualification and production of SoC
devices.
Core Responsibilities:
• Develop and document test plan for new devices.
• Design and debug test SW & HW.
• Debug new silicon.
• Bring quality and cost effective test solution for mass production.
• Coordinate test related activities with both internal and external
group.
• Evaluate new product’s testability and operability.
Qualifications:
• In depth knowledge of Semiconductor Manufacturing Process
• Solid understanding of Electronic Engineering Fundamentals, Design
for Test and Manufacturing Concepts.
• Expertise in Semiconductor Test Methodology.
• Experience working on Digital, Mixed Signal & PMIC Devices with
hands on VLSI ATE experience. System level
experience is a plus.
• Strong Programming skills for writing and debugging test programs.
• Competency in programming with Scripting languages (ie, PERL) and
high level languages (ie, C/C++ or Visual
Basic.)
• Able to work with test equipment (ie, oscilloscope, logic analyzer,
etc)
• 5+ years relevant experience
Education:
BSEE / MSEE is required.
DRAM Product Engineer
Req: 27996948
In this position, you will be ensuring the successful integration of DRAM
memories with SoC devices.
Core Responsibilities:
• Working with design, verification and integration engineers to
ensure memory controller requirements are well
defined and cover the scope of DRAM based corner cases
• Ensuring that the internal and external DRAM silicon and package
level testing meets Apple's requirements
• Developing SW to validate JEDEC DRAM specifications
• Driving the characterization and qualification of DRAM with the
memory vendors
• Generating post-silicon SW diagnostics to root cause parametric
defects
• Debugging RMA material with apparent DRAM related defects
• Collaborating with the DRAM vendors to improve test coverage
• Drive roadmaps and specs of memory vendors for next technology node
devices
Qualifications:
• Excellent communication skills and teamwork abilities
• Expert in DRAM cell architectures
• Expert in DRAM memory organization and periphery design
• Expert in memory test patterns
• Experience with memory controller design and verification
• Experience with LPDDR IO (DDR/DDR2/DDR3) characterization and
qualification
• Experience with state of the art packaging technology (POP, TSV, etc
) and their relationship to DRAM signal/
power integrity
• Previous experience in validation of DRAM devices
• Excellent hardware and software debug skill
• Experience working with the major DRAM memory vendors
• Strong background in computer architecture
• Programming experience in C/C++
• Experience with Verilog/System Verilog
• International Travel Required
Education:
BSEE / MSEE is required.
Embedded Software Automation Engineer
Req: 27996973
Responsible for designing and implementing automated regression testing of
embedded firmware running on
Apple’s SoCs. This candidate will be a member of the SW engineering team
ensuring the quality of the firmware.
Core Responsibilities:
• Architect, design and implementation of automated regression test
environment, including tools and methodologies
• Design and implementation of firmware test cases
• Manage regression hardware lab - configuration, maintenance, and
operation
• Support of functional test environment for firmware regression,
device characterization, and failure analysis
• Generating characterization and analysis reports
• Support the debug of firmware test failures
Qualifications:
• 3+ years of firmware/software embedded development experience
• 3+ years developing automation
• Expertise with Perl scripting or similar scripting language
• Experience working with hardware (e.g., PCBs, SoCs, etc.) in a lab
environment
• Experience using laboratory equipment (e.g., logic analyzer, digital
oscilloscope)
• Experience reading and working from complex schematics
• Knowledge of Tcl, Expect or Lua is a plus
Education:
BSCS, BSEE, BSCE or demonstrated equivalent experience.
Product Engineer
Req: 27996995
In this role, you will be responsible for New Product Introduction(NPI) and
defining problems by identifying failure
modes relates to an SoC.
Core Responsibilities:
• New Product Introduction of SoC and support mass production needs
• Perform data analysis, characterization, and fault isolation to
determine the root cause of the issues
• Work with design, process, and test engineers to identify and
implement corrective actions on both new and
mature products and technologies.
• Define and finalize production screening guard-band specifications
based upon design intent and characterization
result
• Perform statistical data analysis on mass data set
• Perform yield analyses and correlation analyses for all levels of
test - pareto building, statistics, etc.
• Define characterization plan and generate characterization report
Qualifications:
The ideal candidate should have 5+ years of product engineering experience.
• SoC in a high volume environment
• Experience handling ATE test program for characterization and data
collection
• Knowledge to perform statistical data analysis
• Experience in yield management of high volume product
• Ability to setup design of experiment to drive the root cause of the
problem
• Excellent communication skills to work with internal team members
and external suppliers
• Travel is required
Education:
BSEE/MSEE or equivalent is required.
Signal Integrity Engineer
Req: 13696680
We are looking to hiring a Signal Integrity Engineer in a group at Apple
that develops SOCs that will be used in
Apple mobile devices. You will be responsible for the PI and SI for Apple
SOCs covering the spam from package to
board.
Core Responsibilities:
The Signal Integrity Engineer needs to have extensive experience in mobile
product board designs, SI expertise in
Serial links (such as DisplayPort) as well as parallel bus standards (such
as LPDDR2 interface), and power integrity at
package level and as well as board level. Responsibilities includes:
• Work with package design group and board design group to simulate/
characterize package and board PI and
propose and implement design guidelines and product specific design
improvement
• SI simulation and characterization for all high speed parallel and
serial interfaces and provide feedback to package
and board design group for improvement.
• Lab measurement and correlation to close the SI/PI simulation and
validation loop
Qualifications:
The ideal candidate should have experience in the actual product package/
board design and analysis, PI/SI methodology
development, and lab correlation/validation of the simulation results.
• 2+ years of experience
• Familiar with lab equipment, such as VNA, TDR, real-time scope,
spectrum analyzer, and etc
• Deep knowledge in 3D/2D EM simulation tools and transmission line
theory
• High-speed board and PCB design experience
• Team work and good communication skills
Education:
BSEE is required and MSEE/PhD is preferred.
IC Clock Design Engineer
Req: 27439341
In this role, you will be responsible for designing and developing clock
distribution network for SoCs used in Apple
mobile products
Core Responsibilities:
• The role will include being the technically lead for clock design,
methodologies, and implementation.
• Will work in close collaboration with the physical design teams.
• Should have a knowledge of block composition
• Must have a good knowledge of circuit design, transistors operation
• Should have scripting/flow knowledge
Qualifications:
• The ideal candidate should have 5+ years experience in directly
related clock design experience.
• Must be knowledgeable in the areas of block composition, circuit
design and transistors operation.
Education:
BSEE/MSEE is required.
ADC/DAC Analog Designer
Req: 27996955
In this role you will be responsible for designing the sampling modules (
DACs/ADCs) for the Next Generation
Communication IPs.
Core Responsibilities:
• Design best in class sampling modules from circuit to layout for
WLAN and BT technologies in deeply embedded
CMOS processes
• Be a key participants in the decision making process of the best ADC
/ DAC architecture for the program optimizing
the solution in terms of area, power, risk and schedule
• Lead debug of the relevant modules post-Si both on stand alone test
chips and as part of the entire system
Qualifications:
• Excellent overall analog circuit design expertise coupled with
creative problem solving skills and strong understanding
of design tradeoffs, and how those vary as a function of system architecture
, circuit topology and technology
node.
• 8+ years of experience in the ADC and DAC design domain
• Proven experience with designing high performance power-optimized
SAR ADCs in fine line geometries
• Proven experience with designing Sigma Delta converters for wide
band applications (WiFi, WiMax, LTE etc.) from
initial architecture phase to mass production
• Proven experience with designing high performance pipeline ADCs for
wide band applications
• Strong background with state of the art high speed DACs
• Proven Post-Si testing, characterization, and debug capabilities
• Excellent work I/F
• Good system level understanding
Advantages:
• Prior knowledge with BT/WL technologies
• Familiarity with Communication System analysis
• Familiarity with Digital design, RTL, DFT, and Verification
Education:
MSc. is required, PhD is preferred.
High-speed Analog IC Design Engineer
Req: 27996677
Design and develop SerDes IP at the circuit level.
Core Responsibilities:
In this role, the key responsibilities are the following:
• Transistor-level feasibility studies for various blocks in Rx/Tx/Clk
generation
• Transistor-level design of PHY high-speed sub-blocks.
• Drive mask design to implement layout view of designs
• Generation/QA of various IP Kit views/files.
• Defining production/bench-level testplans
• Driving/reviewing yield/lab test results to drive bug fixes.
• Design for ESD compliance
Qualifications:
The ideal candidate should have 5+ years of experience in high-speed serial
links.
• Good knowledge of circuits topologies for use in high-speed Rx/Tx
SerDes PHY
• Good knowledge of Tx/Rx equalization techniques
• Good knowledge of high-speed analog CMOS designs/techniques.
• Experience in C/Matlab/VerilogA modelling
• Strong device physics knowledge as it applies to analog IC designs.
• Good experience in lab testing of high-speed serial links and
defining equipment needs
Education:
BSEE/MSEE is required.
Analog PLL Design Engineer
Req: 27997220
Design/Productize PLLs.
Core Responsibilities:
In this role, the key responsibilities are the following:
• Create overall PLL specifications based on system requirements
• Behavioral modeling of PLL to derive block-level requirements
• Drive mask design to implement layout view of designs
• Top-level simulations to validate top-level integration
• Defining production/bench-level testplans
• Taking lab measurements to validate IP
• Driving/reviewing yield/lab test results to drive bug fixes.
Qualifications:
The ideal candidate should have demonstrated taking chips to production in
the following areas:
• Dual chargepump PLL designs, Fractional-N PLLs, spread-spectrum PLLs
, Digital PLL techniques, etc.
• Good knowledge of bandgaps, bias, opamps, LDOs, feedback and
compensation techniques.
• Experience in VCO design including but not limited to LC VCOs.
The ideal candidate should have demonstrated expertise in the following
areas:
• Demonstrated strong knowledge of loop design to optimize for phase
noise/jitter, lock time, reference spur, area,
power.
• Good knowledge of low noise design techniques
• Good knowledge of high precision techniques in presence of device
mismatch
• Experience in C/Matlab/VerilogA modeling
• Understand device physics and demonstrated ability to apply that to
optimize noise, power, area, frequency of
PLL blocks.
• Good working experience in using spectrum analyzers, oscilloscopes,
signal generators, etc. to validate analog
designs.
• Experience in working with production test engineers to firm up test
plans and design for testability details.
Education:
Requires MSEE with min. 3+ years in related area of expertise or PhD.
Analog IP Validation/Characterization Engineer
Req: 12902654
In this highly visible role, you will perform lab characterization and
validation of embedded circuits; interfacing
with many disciplines to launch the world’s premiere mobile computing chips.
Core Responsibilities:
You will be part of a small team responsible for:
• Bench test, debug, and characterization of embedded on-chip circuits
(PLLs, DLLs, clocks, memory interfaces, and
I/Os).
• In-system PI/SI measurements for correlating with simulation models.
• Debug compliance test failures of standard interfaces (USB, MIPI,
DisplayPort).
• Setup, debug, and maintain lab system test environment.
• Development of bench top characterization tests exercising on-chip
circuits through a combination of FPGA,
JTAG, and analog interfaces
• Development and execution of scripts to automate tests, extract and
store results, and generate reports using
database and analysis tools.
• Preparation of reports related to characterization and debug
• Interface with chip design teams, system HW and SW design teams, ATE
PE
Qualifications:
The ideal candidate will have the following qualifications:
• Min 5 years experience in test development, debug, and reporting
• Expertise in test and script development, PERL / TCL preferred
• Expertise in using electronic measurement equipment
• Expertise with test data analysis platforms and databases
• Expertise in testing/characterizing PLLs, DLLs, SERDES, and memory
interfaces
• Expertise in testing/characterizing control loops for various
voltage regulator topologies (LDOs, bucks, multiphase
bucks).
• Lab skills for soldering/instrumenting systems for test or debug.
• Strong initiative and ownership of responsibilities, productive,
able to meet aggressive deadlines
• Good written and verbal communication skills
• Emphasis on quality and self-checking of scripts, test patterns, and
reports
• Matlab/DSP experience is a plus
Education:
BSEE / MSEE is required.
Analog IP/Silicon Engineer
Req: 9137158
In this highly visible role, you will take ownership of analog IP/silicon
provided by external vendors. Your job is to
assure that the IP/silicon is meeting Apple's high quality standards and
gets flawlessly integrated in industry leading
mobile devices. The role involves working closely with different cross
functional teams within Apple as well as
external vendors. Occasional travel might be required.
Core Responsibilities:
You will be part of a small team responsible for:
• Defining and specifying requirements for analog IP/silicon provided
by external vendors.
• Driving technical discussions with vendors and foundries
• Supervising IP/silicon design, characterization and debug
• Review and sign off of specifications, test plans and
characterization reports
• Supporting Apple system teams with product integration, bring up and
debug
• Interface with chip design teams, system HW and SW design teams, ATE
PE
Qualifications:
The ideal candidate will have the following qualifications:
• Min 7 years experience in analog IC design
• Multidisciplinary; being able to work on a large range of analog
related topics
• Hands-on design expertise in at least 3 of the following areas:
SERDES, PLL, ESD structures, LDOs, Buck converters,
ADC, DAC, Temperature sensors, image sensors
• Experience with advanced CMOS processes (45nm and below)
• Solid understanding of transistor device characteristics
• Solid understanding of power, area and performance trade-off in
mixed-signal designs
• Knowledge of analog IC design flow and tools
• Knowledge of COT design flow is a plus
• Experience with standards like PCI Express, MIPI, USB or DisplayPort
is a plus
• Excellent communication skills
• Strong initiative and ownership of responsibilities, productive,
able to meet aggressive deadlines
• Good written and verbal communication skills
Education:
BSEE / MSEE is required.
Performance Analysis Engineer
Req: 27999409
Location: Austin, TX
In this role you will be responsible for power, performance analysis, tuning
, and debug of Apple’s GPU products. As
part of the Logic design team, you will collaborate closely with other ASIC
Design Engineers, and System Engineers
to study, debug and implement the power consumption and performance of Apple
’s mobile chips in reference and
customer designs.
Core Responsibilities:
• Debug customer-visible system-level functional, power, and
performance issues.
• Validate the functionality and quantify the power savings and
performance benefit of the features and algorithms
implemented in our HW and SW.
• Perform measurements to characterize and tune the power and
performance of reference platforms and next
generation designs using real applications and usage models.
• Conduct directed studies and contribute solutions to functional
power and performance challenges unique to
mobile SOCs that are aimed at driving the architecture of next generation
mobile products via measurements,
simulations, benchmarking, or competitive analysis
Qualifications:
• 3 years or more of Perl or Python experience.
• Experience and familiarity with systems software, operating systems,
as well as intuition for user level application
interactions.
• Experience in characterizing power and performance, doing comparison
studies, and debugging power/
performance issues.
• Experience with creating, debugging and tuning power and performance
models
• Ability to distill questions about complex and concurrent systems
into simple testable statements.
• ARM or other microprocessor experience.
• 3D GPU experience/ Video experience
• Experience with chip backbone and interconnect architectures, buses,
I/O hubs, I/O systems, storage, networking,
media processing, etc.
Education:
MS in EE/CS/ECS or related technical field or equivalent. Ideal focus on
computer architecture.
Silicon Vendor Management Engineer
Req: 26561914
The System Silicon Group provides critical custom silicon for Apple products
including iPhone, iPad, iPod, AppleTV,
and associated accessories. These ICs are critical in enabling the
differentiation and exceptional quality Apple
products are known for. Apple is looking for a world-class Silicon Manager
to work with cross-functional teams
and external vendors to develop and productize the next generation of
devices. Additionally, this role is expected
to drive crisis management and communicate the status of programs to
executive staff.
Core Responsibilities:
As a part of the team responsible for the delivery of high-quality, on-time
silicon, you will have responsibilities
spanning all aspects of silicon design:
• Working with the Systems and Platform teams to establish silicon
requirements.
• Leading efforts to develop, integrate, characterize, and test
devices including power regulators, video converters,
chargers, backlight drivers, boost, audio, sensors, video converters, buffer
/level shifters, and the associated control
circuits.
• Delivering first revision functional silicon and production worthy
silicon per system requirements.
• Working with vendors and internal subject matter experts to ensure
state-of-the-art design practices, methodologies
and processes are in place and producing quality results.
• Interfacing with vendors and internal product teams to coordinate
silicon validation and roadmap development
• Ensuring designs are properly verified, validated, and tested for
long-term reliability.
• Managing schedules, supporting cross-functional engineering efforts,
and providing regular project status updates
for executive review.
Qualifications:
The ideal candidate will have 10+ years of experience leading mixed-signal
silicon for complex system designs:
• Knowledge about industrial standards and practices in appropriate
technologies.
• ASIC and/or Mixed-Signal design experience across product life cycle
including chip definition, design, tapeout,
bring-up, and productization.
• Design knowledge of board level considerations, including component
selection, PCB layout, and device characterization.
• Solid understand of the analog and digital fundamentals, design
tools and design techniques.
• Experience in the fields of packaging and reliability for associated
devices.
• Hands-on lab experience.
• Experience as a design manager in each area is a plus.
Education:
BSEE / MSEE is required.
Senior Product Engineer
Req: 26625601
In this role, you will be responsible for analyzing and solving problems by
identifying failure modes and quantity of
material affected as it relates to analog and digital ICs.
Core Responsibilities:
• Perform data analysis, characterization, and fault isolation to
determine root cause of issues.
• Work with design, process, and test engineers to identify and
implement corrective actions on both new and
mature products and technologies.
• Define and finalize production screening guard-band specifications
based upon design intent and characterization
result.
• Perform statistical data analysis on mass data set.
• Perform yield analyses and correlation analyses for all levels of
test -- pareto building, statistics, etc.
• Define characterization plan and generate characterization report.
Qualifications:
The ideal candidate will have 10+ years of product engineering experience
for complex system designs:
• Analog and digital IC evaluation report analysis.
• ATE characterization and data collection test program experience.
• Analog and digital IC high volume manufacturing experience.
• Statistical data analysis knowledge.
• High volume product yield management.
• Ability to define and direct design of experiment for root cause
determination.
• Excellent communication skills to work with internal team members
and external suppliers.
• Travel is required.
Education:
BSEE / MSEE is required.
VLSI Design Manager
Req: 26537018
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish.
The System Silicon Group provides critical devices for all mobile products
include iPhone, iPad, iPod, and AppleTV.
Apple is looking for a world-class manager and leader to work with cross-
functional teams and external vendors to
develop and productize the next generation of devices.
Core Responsibilities:
As a Silicon manager owning the delivery of silicon, you will have
responsibilities spanning all aspects of silicon
design:
• Working with the Systems and Platform teams to establish silicon
requirements
• Driving a roadmap to provide new, proven IP for inclusion in
production silicon
• Delivering first revision function silicon and production worthy
silicon per system requirements.
• Working with vendors to ensure state-of-the-art design practices,
methodologies and processes are in place and
producing quality results.
• Ensuring designs are properly verified, validated, and tested for
long-term reliability.
• Managing schedules and supporting cross-functional engineering
efforts.
Qualifications:
• The ideal candidate will have 5+ years of management experience
• 10+ years of experience leading silicon for complex system designs:
• Knowledge about industrial standards and practices in silicon
• Design knowledge of board level considerations, including component
selection, PCB layout, and device characterization
• Solid understand of the analog & digital fundamentals, design tools
and design techniques.
Education:
BS / MS / Ph.D in EE or CS is required.
Analog Chip Development Engineer
Req: 22069825
Imagine what you could do here. At Apple, great ideas have a way of becoming
great products, services, and customer
experiences very quickly. Bring passion and dedication to your job and there
's no telling what you could
accomplish.
The System Silicon Group provides critical custom silicon for all mobile
products including iPhone, iPad, iPod, and
AppleTV. Apple is looking for a world-class analog design leader to work
with cross-functional teams and external
vendors to define, develop and productize the next generation of devices.
Core Responsibilities:
As a part of the team responsible for the delivery of high-quality, on-time
silicon, you will have responsibilities
spanning all aspects of silicon design:
• Working with the Systems and Platform teams to establish silicon
requirements
• Leading efforts to develop, integrate, characterize, and test
devices including power regulators, video converters,
chargers, backlight drivers, boost, audio, sensors, video converters, buffer
/level shifters and the associated control
circuits.
• Delivering first revision functional silicon and production worthy
silicon per system requirements.
• Working with vendors to ensure state-of-the-art design practices,
methodologies and processes are in place and
producing quality results.
• Ensuring designs are properly verified, validated, and tested for
long-term reliability.
• Managing schedules and supporting cross-functional engineering
efforts.
Qualifications:
The ideal candidate will have 10+ years of experience leading mixed-signal
silicon for complex system designs:
• Knowledge about industrial standards and practices in appropriate
technologies.
• Design experience in all aspects of power/video/battery/backlight/
audio devices
• Design knowledge of board level considerations, including component
selection, PCB layout, and device characterization.
• Solid understand of the analog & digital fundamentals, design tools
and design techniques.
• Experience in the fields of packaging and reliability for associated
devices.
• Hands-on lab experience.
• Experience as a design manager in each area is a plus.
Education:
BS / MS / Ph.D in EE or CS is required.
Unit Level Design Verification Engineer
Req: 26864010
In this highly visible role, the Functional Verification Engineer will be
responsible for the pre-silicon verification of
embedded graphics cores.
Core Responsibilities:
• Support the design through RTL development and into production
• Develop verification plans, create verification test bench
components, generate tests, run simulations, and debug
design issues
• Create functional coverage points, analyze coverage, and enhance
test environment to target coverage holes
• Provide in-depth knowledge of architecture, implementation,
verification, and debug
• Utilize skills including UNIX and Perl to create efficient,
automated verification flows
• Apply knowledge of hardware description languages (VHDL/Verilog),
hardware verification languages
(SystemVerilog/UVM/OVM), and logic simulators to verify complex designs
Qualifications:
• Verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL;
Specman experience is a plus
• Expertise with various HDL simulators and waveform viewers like
NCSIM, ModelSim, VCS, DVE, Verdi
• Perl, Shell scripting, Makefiles, TCL
• Good knowledge of Computer Architecture, General Purpose
Microprocessor and Memory sub-system microarchitecture
• Experience defining coverage space, writing coverage model,
analyzing results
• Graphics architecture and programming (OpenGL/OpenCL) is a plus
Education:
BSEE/MSEE 3+ years of experience preferred.
Logic Design Engineer
Req: 26318805
Location: Orlando, FL
In this role, the Logic Designer will be responsible for delivering quality
IP in order to meet project functional, timing,
area, and power goals.
Core Responsibilities:
This individual will collaborate with the architecture team, functional
verification team, and physical design team
• The responsibilities encompass all phases of design including
• micro-architecture definition
• specification
• implementation
• simulation
• synthesis
Qualifications:
• 5+ yrs of industry experience
• Knowledgeable in modern design techniques and energy-efficient/low
power logic design
• Strong background in computer architecture including one or more of:
• high-speed CMOS processor and controller blocks like cache
controllers, bus-interface- subsystems, integer and
floating point numeric units, digital filters, graphics processors, crossbar
fabrics and other high-speed data-path
and control units.
• Expertise in logic optimization, synthesis, timing analysis, floor-
planning
• Fluent with RTL Verilog/VHDL syntax and hardware modeling issues
• Familiarity with logic simulation and debug environments as well as
formal verification.
• Ability to work well in a team and be productive under aggressive
schedules.
• Should exhibit excellent communications skills, and be self-
motivated and well organized.
Education:
PHD/MSEE preferred; or BSEE plus equivalent level of experience.
Logic Design Engineer
Req: 23455032
In this role, the Logic Designer will be responsible for delivering quality
IP in order to meet project functional, timing,
area, and power goals.
Core Responsibilities:
This individual will collaborate with the architecture team, functional
verification team, and physical design team
• The responsibilities encompass all phases of design including
• micro-architecture definition
• specification
• implementation
• simulation
• synthesis
Qualifications:
• 5+ yrs of industry experience
• Knowledgeable in modern design techniques and energy-efficient/low
power logic design
• Strong background in computer architecture including one or more of:
• high-speed CMOS processor and controller blocks like cache
controllers, bus-interface- subsystems, integer and
floating point numeric units, digital filters, graphics processors, crossbar
fabrics and other high-speed data-path
and control units.
• Expertise in logic optimization, synthesis, timing analysis, floor-
planning
• Fluent with RTL Verilog/VHDL syntax and hardware modeling issues
• Familiarity with logic simulation and debug environments as well as
formal verification.
• Ability to work well in a team and be productive under aggressive
schedules.
• Should exhibit excellent communications skills, and be self-
motivated and well organized.
Education:
PHD/MSEE preferred; or BSEE plus equivalent level of experience.
GPU Micro Architect
Req: 25365208
Core Responsibilities:
In this highly visible role, you will be responsible for development of
power efficient, high performance 3D graphics
processors
Qualifications:
The ideal candidate will possess a Master’s degree and ten plus years of
experience in graphics micro-architecture.
• OpenGL application programming and graphics driver tuning experience
• Expertise in performance measurement and analysis of GPU micro-
architectures and complex 3D scene workloads
• Proficiency with vendor synthesis tools
• Experience designing/analyzing hardware and software graphics
pipelines
• Expertise in floating-point/numerics with regards to graphics image
quality
• Expert in several major sub-units in a high-performance 3D graphics
processor.
• Possesses understanding of processor performance intricacies across
a broad set of workloads.
Education:
MSEE/CE required.
Logic Implementation Engineer
Req: 28006913
Location: Orlando, FL
This position will be responsible for all phases of front-end logic design,
with the primary focus on RTL to gatelevel
netlist creation.
Core Responsibilities:
• Optimize designs to achieve power, area, timing goals
• Simulation/debug of large complex designs
• Collaborate effectively with different functional teams
Qualifications:
The ideal candidate will have 5 years of hands on experience in front end
logic design:
• Proven expertise in advanced synthesis techniques to achieve
aggressive power, area, and timing goals.
• Ability to optimize designs with logically equivalent RTL
modifications.
• Proficiency in: static timing analysis, Verilog/VHDL, formal
verification, lint checks, multi-clock and power domain
designs.
• Familiarity with simulation and debugging tools.
• Insight into physical design implications: floor-planning, placement
, congestion, and setup/hold timing closure.
• Experience with DFT insertion, multi-mode timing constraints, and
ECO implementation.
• Knowledge of architecture and micro-architecture of CPUs, GPUs, or
DSPs desirable.
Education:
Phd/MSEE, or BSEE with relevant industry experience preferred.
Logic Implementation Engineer
Req: 28007053
This position will be responsible for all phases of front-end logic design,
with the primary focus on RTL to gatelevel
netlist creation.
Core Responsibilities:
• Optimize designs to achieve power, area, timing goals
• Simulation/debug of large complex designs
• Collaborate effectively with different functional teams
Qualifications:
The ideal candidate will have 5 years of hands on experience in front end
logic design:
• Proven expertise in advanced synthesis techniques to achieve
aggressive power, area, and timing goals.
• Ability to optimize designs with logically equivalent RTL
modifications.
• Proficiency in: static timing analysis, Verilog/VHDL, formal
verification, lint checks, multi-clock and power domain
designs.
• Familiarity with simulation and debugging tools.
• Insight into physical design implications: floor-planning, placement
, congestion, and setup/hold timing closure.
• Experience with DFT insertion, multi-mode timing constraints, and
ECO implementation.
• Knowledge of architecture and micro-architecture of CPUs, GPUs, or
DSPs desirable.
Education:
Phd/MSEE, or BSEE with relevant industry experience preferred.
Performance Analysis Engineer
Req: 28007345
Location: Orlando, FL
In this role you will be responsible for power, performance analysis, tuning
, and debug of Apple’s GPU products. As
part of the Logic design team, you will collaborate closely with other ASIC
Design Engineers, and System Engineers
to study, debug and implement the power consumption and performance of Apple
’s mobile chips in reference and
customer designs.
Core Responsibilities:
• Debug customer-visible system-level functional, power, and
performance issues.
• Validate the functionality and quantify the power savings and
performance benefit of the features and algorithms
implemented in our HW and SW.
• Perform measurements to characterize and tune the power and
performance of reference platforms and next
generation designs using real applications and usage models.
• Conduct directed studies and contribute solutions to functional
power and performance challenges unique to
mobile SOCs that are aimed at driving the architecture of next generation
mobile products via measurements,
simulations, benchmarking, or competitive analysis
Qualifications:
• 3 years or more of Perl or Python experience.
• Experience and familiarity with systems software, operating systems,
as well as intuition for user level application
interactions.
• Experience in characterizing power and performance, doing comparison
studies, and debugging power/
performance issues.
• Experience with creating, debugging and tuning power and performance
models
• Ability to distill questions about complex and concurrent systems
into simple testable statements.
• ARM or other microprocessor experience.
• 3D GPU experience/ Video experience
• Experience with chip backbone and interconnect architectures, buses,
I/O hubs, I/O systems, storage, networking,
media processing, etc.
Education:
MS in EE/CS/ECS or related technical field or equivalent. Ideal focus on
computer architecture.
Performance Analysis Engineer
Req: 28007285
In this role you will be responsible for power, performance analysis, tuning
, and debug of Apple’s GPU products. As
part of the Logic design team, you will collaborate closely with other ASIC
Design Engineers, and System Engineers
to study, debug and implement the power consumption and performance of Apple
’s mobile chips in reference and
customer designs.
Core Responsibilities:
• Debug customer-visible system-level functional, power, and
performance issues.
• Validate the functionality and quantify the power savings and
performance benefit of the features and algorithms
implemented in our HW and SW.
• Perform measurements to characterize and tune the power and
performance of reference platforms and next
generation designs using real applications and usage models.
• Conduct directed studies and contribute solutions to functional
power and performance challenges unique to
mobile SOCs that are aimed at driving the architecture of next generation
mobile products via measurements,
simulations, benchmarking, or competitive analysis
Qualifications:
• 3 years or more of Perl or Python experience.
• Experience and familiarity with systems software, operating systems,
as well as intuition for user level application
interactions.
• Experience in characterizing power and performance, doing comparison
studies, and debugging power/
performance issues.
• Experience with creating, debugging and tuning power and performance
models
• Ability to distill questions about complex and concurrent systems
into simple testable statements.
• ARM or other microprocessor experience.
• 3D GPU experience/ Video experience
• Experience with chip backbone and interconnect architectures, buses,
I/O hubs, I/O systems, storage, networking,
media processing, etc.
Education:
MS in EE/CS/ECS or related technical field or equivalent. Ideal focus on
computer architecture.
Top Level Design Verification and Debug Engineer
Req: 28006574
Location: Orlando, FL
In this highly visible role, the Top Level Design Verification and Debug
Engineer will be responsible for the presilicon
verification of embedded graphics cores.
Core Responsibilities:
• Support the design through RTL development and into production
• Develop verification plans, create verification test bench
components, generate tests, run simulations, and debug
design issues
• Create functional coverage points, analyze coverage, and enhance
test environment to target coverage holes
• Provide in-depth knowledge of architecture, implementation,
verification, and debug
• Utilize skills including UNIX and Perl to create efficient,
automated verification flows
• Apply knowledge of hardware description languages (VHDL/Verilog),
hardware verification languages
(Specman/System Verilog), and logic simulators to verify complex designs
Qualifications:
• Verification language such as Specman, SystemVerilog, Verilog/VHDL
• Expertise with various HDL simulators and waveform viewers like
NCSIM, ModelSim, VCS, DVE, Verdi
• Perl, Shell scripting, Makefiles, TCL
• Good knowledge of Computer Architecture, General Purpose
Microprocessor and Memory sub-system microarchitecture
• Experience defining coverage space, writing coverage model,
analyzing results
Education:
BSEE/MSEE 3+ years of experience preferred.
Top Level Design Verification and Debug Engineer
Req: 28006871
In this highly visible role, the Top Level Design Verification and Debug
Engineer will be responsible for the presilicon
verification of embedded graphics cores.
Core Responsibilities:
• Support the design through RTL development and into production
• Develop verification plans, create verification test bench
components, generate tests, run simulations, and debug
design issues
• Create functional coverage points, analyze coverage, and enhance
test environment to target coverage holes
• Provide in-depth knowledge of architecture, implementation,
verification, and debug
• Utilize skills including UNIX and Perl to create efficient,
automated verification flows
• Apply knowledge of hardware description languages (VHDL/Verilog),
hardware verification languages
(Specman/System Verilog), and logic simulators to verify complex designs
Qualifications:
• Verification language such as Specman, SystemVerilog, Verilog/VHDL
• Expertise with various HDL simulators and waveform viewers like
NCSIM, ModelSim, VCS, DVE, Verdi
• Perl, Shell scripting, Makefiles, TCL
• Good knowledge of Computer Architecture, General Purpose
Microprocessor and Memory sub-system microarchitecture
• Experience defining coverage space, writing coverage model,
analyzing results
Education:
BSEE/MSEE 3+ years of experience preferred.
Design Verification Engineer
Req: 28016213
Location: Austin, TX
In this highly visible role, as part of a highly talented team you will be
at the heart of the chip design effort interfacing
with all disciplines (vertical product model) with critical impact in
getting functional products to millions of
customers quickly.
Core Responsibilities:
You will be responsible for ensuring the quality of the SOC & are expected
to:
• Work closely with the team, review specifications, develop
attributes, tests & coverage plans, define methodology
& test benches.
• Work closely with design & micro-architecture teams to understand
the functional & performance goals of the
design.
• Stay abreast with design specs, conduct test plan reviews, develop
block/full chip tests & triage of failures.
• Have strong communication skills combined with good team-oriented
approaches to lead the verification efforts
in a specific area of the design.
• Support gate level functional verification, run regressions, manage
bug tracking, analyze code & functional coverage...
etc.
• Work independently & manage deliverables to align with the project
goals plus support cross-functional engineering
efforts.
Qualifications:
The ideal candidate will have more than 5 years of Verification experience:
• Advanced knowledge of CPU & SOC architecture/design & in-depth
knowledge of verification flow.
• Experience with low-level programming of complex computer systems in
C/C++/assembly.
• Familiarity with verification environments, VMM, System Verilog is a
plus.
• Knowledge of industry standard interfaces, good understanding of
Verilog, Verilog simulator and debug.
• Clear understanding of constrained random verification process,
functional coverage, code coverage, assertion
methodology & philosophy.
• Knowledge of formal, hardware acceleration all plusses.
• Should be a team player with excellent communication skills and the
desire to take on diverse challenges.
Education:
BSEE / MSEE or MSCE.
Design Verification Engineer
Req: 18543685
In this highly visible role, as part of a highly talented team you will be
at the heart of the chip design effort interfacing
with all disciplines (vertical product model) with critical impact in
getting functional products to millions of
customers quickly.
Core Responsibilities:
You will be responsible for ensuring the quality of the SOC & are expected
to:
• Work closely with the team, review specifications, develop
attributes, tests & coverage plans, define methodology
& test benches.
• Work closely with design & micro-architecture teams to understand
the functional & performance goals of the
design.
• Stay abreast with design specs, conduct test plan reviews, develop
block/full chip tests & triage of failures.
• Have strong communication skills combined with good team-oriented
approaches to lead the verification efforts
in a specific area of the design.
• Support gate level functional verification, run regressions, manage
bug tracking, analyze code & functional coverage...
etc.
• Work independently & manage deliverables to align with the project
goals plus support cross-functional engineering
efforts.
Qualifications:
The ideal candidate will have more than 5 years of Verification experience:
• Advanced knowledge of CPU & SOC architecture/design & in-depth
knowledge of verification flow.
• Experience with low-level programming of complex computer systems in
C/C++/assembly.
• Familiarity with verification environments, VMM, System Verilog is a
plus.
• Knowledge of industry standard interfaces, good understanding of
Verilog, Verilog simulator and debug.
• Clear understanding of constrained random verification process,
functional coverage, code coverage, assertion
methodology & philosophy.
• Knowledge of formal, hardware acceleration all plusses.
• Should be a team player with excellent communication skills and the
desire to take on diverse challenges.
Education:
BSEE / MSEE or MSCE.
Site Manager
Req: 27994768
Location: Orlando
Manager will be responsible for leading the Orlando GPU team to deliver high
quality IP to specification and on
schedule.
Core Responsibilities:
• Recruiting, hiring and building a world-class GFX IP development
team
• Growing/mentoring an effective leadership and team management
structure
• Effective collaboration with cross-site teams including architecture
, design, validation, and physical implementation
• Driving, tracking and executing GFX IP development owned by Site
from inception to retirement
• Owning regular personnel reviews, compensation planning/advocacy and
communication for the Site
• Representing Site within larger Apple organization in Austin and San
francisco bay area
Qualifications:
• 10+ years proven experience leading high performance GFX (or
equivalent complexity) IP development teams
• 5+ years proven experience building/hiring medium/large (30+)
complex ASIC IP development teams
• Excellent personnel management, mentoring, team building and hiring
abilities
• Proven ability to manage parallel project efforts including
effective resource/schedule planning & tracking
• Excellent written/verbal communication and project management skills
• Experience with GFX Architecture/Design, GFX APIs and overall GFX
development is a significant plus
• Ability to work well in a cross-site team and be productive under
aggressive schedules
Education:
BS/MS or equivalent experience.
Site Manager
Req: 23606101
Manager will be responsible for leading the San francisco bay area GPU team
to deliver high quality IP to specification and on
schedule.
Core Responsibilities:
• Recruiting, hiring and building a world-class GFX IP development
team
• Growing/mentoring an effective leadership and team management
structure
• Effective collaboration with cross-site teams including architecture
, design, validation, and physical implementation
• Driving, tracking and executing GFX IP development owned by Site
from inception to retirement
• Owning regular personnel reviews, compensation planning/advocacy and
communication for the Site
• Representing Site within larger Apple organization in Austin and San
francisco bay area
Qualifications:
• 10+ years proven experience leading high performance GFX (or
equivalent complexity) IP development teams
• 5+ years proven experience building/hiring medium/large (30+)
complex ASIC IP development teams
• Excellent personnel management, mentoring, team building and hiring
abilities
• Proven ability to manage parallel project efforts including
effective resource/schedule planning & tracking
• Excellent written/verbal communication and project management skills
• Experience with GFX Architecture/Design, GFX APIs and overall GFX
development is a significant plus
• Ability to work well in a cross-site team and be productive under
aggressive schedules
Education:
BS/MS or equivalent experience.
1 (共1页)
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