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发帖数: 28 | 1 My group has multiple job openings for ASIC Physical Design Engineer (Back-
end) in a processor group in Bay area. If you're interested, please contact
me
through BBS email system first. at least 1 year experience required. No NCG
at this time.
VLSI/Physical Design Engineer
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
RESPONSIBILITIES:
• Ownership of design floor planning, synthesis, DFT, place and
route, clock and power distribution, static timing analysis, signal
integrity analysis, physical verification.
• Contribute to developing physical design methodologies and RTL to
GDS flow automation. |
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